Lines Matching defs:GATE_DIV
143 #define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
406 GATE_DIV(BM1880_CLK_50M_A53, "clk_50m_a53", "clk_fpll",
409 GATE_DIV(BM1880_CLK_EFUSE, "clk_efuse", "clk_fpll",
412 GATE_DIV(BM1880_CLK_EMMC, "clk_emmc", "clk_fpll",
415 GATE_DIV(BM1880_CLK_100K_EMMC, "clk_100k_emmc", "clk_div_12m_usb",
418 GATE_DIV(BM1880_CLK_SD, "clk_sd", "clk_fpll",
421 GATE_DIV(BM1880_CLK_100K_SD, "clk_100k_sd", "clk_div_12m_usb",
424 GATE_DIV(BM1880_CLK_500M_ETH0, "clk_500m_eth0", "clk_fpll",
427 GATE_DIV(BM1880_CLK_500M_ETH1, "clk_500m_eth1", "clk_fpll",
431 GATE_DIV(BM1880_CLK_GPIO_DB, "clk_gpio_db", "clk_div_12m_usb",
434 GATE_DIV(BM1880_CLK_SDMA_AUD, "clk_sdma_aud", "clk_fpll",
437 GATE_DIV(BM1880_CLK_JPEG_AXI, "clk_jpeg_axi", "clk_fpll",
440 GATE_DIV(BM1880_CLK_NF, "clk_nf", "clk_fpll",
443 GATE_DIV(BM1880_CLK_TPU_AXI, "clk_tpu_axi", "clk_spll",
446 GATE_DIV(BM1880_CLK_125M_USB, "clk_125m_usb", "clk_fpll",
449 GATE_DIV(BM1880_CLK_33K_USB, "clk_33k_usb", "clk_div_12m_usb",
452 GATE_DIV(BM1880_CLK_VIDEO_AXI, "clk_video_axi", "clk_fpll",
455 GATE_DIV(BM1880_CLK_VPP_AXI, "clk_vpp_axi", "clk_fpll",
460 GATE_DIV(BM1880_CLK_AXI2, "clk_axi2", "clk_fpll",
463 GATE_DIV(BM1880_CLK_AXI3, "clk_axi3", "clk_mux_rv",
466 GATE_DIV(BM1880_CLK_AXI4, "clk_axi4", "clk_fpll",
469 GATE_DIV(BM1880_CLK_AXI5, "clk_axi5", "clk_fpll",