Lines Matching defs:gate
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
55 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
56 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
57 [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
58 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
59 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
60 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
61 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
62 [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
63 [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
64 [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
65 [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
66 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
67 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
68 [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
69 [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
70 [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
71 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
72 [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
186 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
187 u32 clk = BIT(gate->clock_idx);
188 u32 rst = BIT(gate->reset_idx);
189 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
198 if (gate->reset_idx >= 0) {
199 regmap_read(gate->map, ASPEED_RESET_CTRL, ®);
204 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);
211 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
213 u32 clk = BIT(gate->clock_idx);
214 u32 rst = BIT(gate->reset_idx);
217 spin_lock_irqsave(gate->lock, flags);
220 spin_unlock_irqrestore(gate->lock, flags);
224 if (gate->reset_idx >= 0) {
226 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
233 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
234 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
236 if (gate->reset_idx >= 0) {
241 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);
244 spin_unlock_irqrestore(gate->lock, flags);
251 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
253 u32 clk = BIT(gate->clock_idx);
256 spin_lock_irqsave(gate->lock, flags);
258 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0;
259 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
261 spin_unlock_irqrestore(gate->lock, flags);
350 struct aspeed_clk_gate *gate;
355 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
356 if (!gate)
365 gate->map = map;
366 gate->clock_idx = clock_idx;
367 gate->reset_idx = reset_idx;
368 gate->flags = clk_gate_flags;
369 gate->lock = lock;
370 gate->hw.init = &init;
372 hw = &gate->hw;
375 kfree(gate);
443 /* SD/SDIO clock divider and gate */