Lines Matching defs:init
1343 struct clk_init_data init;
1346 memset(&init, 0, sizeof(init));
1349 init.parent_names = &cprman->real_parent_names[0];
1350 init.num_parents = 1;
1351 init.name = pll_data->name;
1352 init.ops = &bcm2835_pll_clk_ops;
1353 init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
1361 pll->hw.init = &init;
1377 struct clk_init_data init;
1390 memset(&init, 0, sizeof(init));
1392 init.parent_names = ÷r_data->source_pll;
1393 init.num_parents = 1;
1394 init.name = divider_name;
1395 init.ops = &bcm2835_pll_divider_clk_ops;
1396 init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
1407 divider->div.hw.init = &init;
1438 struct clk_init_data init;
1457 memset(&init, 0, sizeof(init));
1458 init.parent_names = parents;
1459 init.num_parents = clock_data->num_mux_parents;
1460 init.name = clock_data->name;
1461 init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
1468 init.flags |= CLK_SET_RATE_PARENT;
1471 init.ops = &bcm2835_vpu_clock_clk_ops;
1473 init.ops = &bcm2835_clock_clk_ops;
1474 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1480 init.flags &= ~CLK_IS_CRITICAL;
1489 clock->hw.init = &init;