Lines Matching defs:clock
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
38 #include <dt-bindings/clock/bcm2835.h>
321 * Real names of cprman clock parents looked up through
323 * parent_names[] arrays for clock registration.
345 /* Does a cycle of measuring a clock through the TCNT clock, which may
724 /* Unmask the reference clock from the oscillator. */
913 * fake it by having some fixed shifts preceding it in the clock tree,
929 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
930 struct bcm2835_cprman *cprman = clock->cprman;
931 const struct bcm2835_clock_data *data = clock->data;
940 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
941 const struct bcm2835_clock_data *data = clock->data;
951 /* different clamping limits apply for a mash clock */
972 static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
976 const struct bcm2835_clock_data *data = clock->data;
984 * the bits are populated in any given clock.
1011 * If increasing a clock by less than 0.1% changes it
1023 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1024 struct bcm2835_cprman *cprman = clock->cprman;
1025 const struct bcm2835_clock_data *data = clock->data;
1034 rate = bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1042 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1044 struct bcm2835_cprman *cprman = clock->cprman;
1045 const struct bcm2835_clock_data *data = clock->data;
1051 clk_hw_get_name(&clock->hw));
1060 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1061 struct bcm2835_cprman *cprman = clock->cprman;
1062 const struct bcm2835_clock_data *data = clock->data;
1070 bcm2835_clock_wait_busy(clock);
1075 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1076 struct bcm2835_cprman *cprman = clock->cprman;
1077 const struct bcm2835_clock_data *data = clock->data;
1086 /* Debug code to measure the clock once it's turned on to see
1103 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1104 struct bcm2835_cprman *cprman = clock->cprman;
1105 const struct bcm2835_clock_data *data = clock->data;
1114 * In principle it is recommended to stop/start the clock first,
1116 * clock this requirement should be take care of by the
1146 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1147 struct bcm2835_cprman *cprman = clock->cprman;
1148 const struct bcm2835_clock_data *data = clock->data;
1159 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1165 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1168 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1184 /* clamp to min divider of 2 if we're dealing with a mash clock */
1223 * Select parent clock that results in the closest but lower rate
1231 * Don't choose a PLLC-derived clock as our parent
1235 * prior notification to our clock consumer.
1264 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1265 struct bcm2835_cprman *cprman = clock->cprman;
1266 const struct bcm2835_clock_data *data = clock->data;
1275 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1276 struct bcm2835_cprman *cprman = clock->cprman;
1277 const struct bcm2835_clock_data *data = clock->data;
1297 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1298 struct bcm2835_cprman *cprman = clock->cprman;
1299 const struct bcm2835_clock_data *data = clock->data;
1325 * The VPU clock can never be disabled (it doesn't have an ENABLE
1326 * bit), so it gets its own set of clock ops.
1437 struct bcm2835_clock *clock;
1445 * actual clock-output-name of the parent.
1476 /* If the clock wasn't actually enabled at boot, it's not
1483 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1484 if (!clock)
1487 clock->cprman = cprman;
1488 clock->data = clock_data;
1489 clock->hw.init = &init;
1491 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1494 return &clock->hw;
1516 /* assignment helper macros for different clock types */
1572 * Restrict clock sources for the PCM peripheral to the oscillator and
1669 * (Compact Camera Port 2) transmitter clock.
1729 /* PLLB is used for the ARM's clock. */
1758 * PLLC is the core PLL, used to drive the core VPU clock.
1885 * PLLH is used to supply the pixel clock or the AUX clock for the
1940 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1950 * Used for a 1Mhz clock for the system clocksource, and also used
1998 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
2018 * VPU clock. This doesn't have an enable bit, since it drives
2075 /* Arasan EMMC clock */
2085 /* EMMC2 clock (only available for BCM2711) */
2179 /* TV encoder clock. Only operating frequency is 108Mhz. */
2234 * non-stop vpu clock.
2244 * Permanently take a reference on the parent of the SDRAM clock.
2248 * periodically switches the SDRAM to using our CM clock to do PVT
2352 MODULE_DESCRIPTION("BCM2835 clock driver");