Lines Matching refs:core
41 struct sam9x60_pll_core core;
48 struct sam9x60_pll_core core;
55 #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core)
56 #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core)
77 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
78 struct sam9x60_frac *frac = to_sam9x60_frac(core);
84 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
86 struct sam9x60_frac *frac = to_sam9x60_frac(core);
87 struct regmap *regmap = core->regmap;
91 spin_lock_irqsave(core->lock, flags);
94 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
96 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
97 cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
99 if (sam9x60_frac_pll_ready(regmap, core->id) &&
104 if (core->characteristics->upll)
111 (frac->mul << core->layout->mul_shift) |
112 (frac->frac << core->layout->frac_shift));
114 if (core->characteristics->upll) {
130 AT91_PMC_PLL_UPDT_UPDATE | core->id);
138 AT91_PMC_PLL_UPDT_UPDATE | core->id);
140 while (!sam9x60_pll_ready(regmap, core->id))
144 spin_unlock_irqrestore(core->lock, flags);
151 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
153 return sam9x60_frac_pll_set(core);
158 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
159 struct regmap *regmap = core->regmap;
162 spin_lock_irqsave(core->lock, flags);
165 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
169 if (core->characteristics->upll)
175 AT91_PMC_PLL_UPDT_UPDATE | core->id);
177 spin_unlock_irqrestore(core->lock, flags);
182 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
184 return sam9x60_pll_ready(core->regmap, core->id);
187 static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
192 struct sam9x60_frac *frac = to_sam9x60_frac(core);
231 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
233 return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false);
239 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
241 return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
247 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
248 struct sam9x60_frac *frac = to_sam9x60_frac(core);
249 struct regmap *regmap = core->regmap;
254 ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
258 spin_lock_irqsave(core->lock, irqflags);
261 core->id);
263 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
264 cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
270 (frac->mul << core->layout->mul_shift) |
271 (frac->frac << core->layout->frac_shift));
275 AT91_PMC_PLL_UPDT_UPDATE | core->id);
284 AT91_PMC_PLL_UPDT_UPDATE | core->id);
286 while (!sam9x60_pll_ready(regmap, core->id))
290 spin_unlock_irqrestore(core->lock, irqflags);
297 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
298 struct sam9x60_frac *frac = to_sam9x60_frac(core);
300 frac->pms.status = sam9x60_pll_ready(core->regmap, core->id);
307 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
308 struct sam9x60_frac *frac = to_sam9x60_frac(core);
311 sam9x60_frac_pll_set(core);
337 static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
340 struct regmap *regmap = core->regmap;
341 u32 ena_msk = enable ? core->layout->endiv_mask : 0;
342 u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0;
345 core->layout->div_mask | ena_msk,
346 (div << core->layout->div_shift) | ena_val);
350 AT91_PMC_PLL_UPDT_UPDATE | core->id);
352 while (!sam9x60_pll_ready(regmap, core->id))
356 static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
358 struct sam9x60_div *div = to_sam9x60_div(core);
359 struct regmap *regmap = core->regmap;
363 spin_lock_irqsave(core->lock, flags);
365 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
367 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
370 if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
373 sam9x60_div_pll_set_div(core, div->div, 1);
376 spin_unlock_irqrestore(core->lock, flags);
383 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
385 return sam9x60_div_pll_set(core);
390 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
391 struct regmap *regmap = core->regmap;
394 spin_lock_irqsave(core->lock, flags);
397 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
400 core->layout->endiv_mask, 0);
404 AT91_PMC_PLL_UPDT_UPDATE | core->id);
406 spin_unlock_irqrestore(core->lock, flags);
411 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
412 struct regmap *regmap = core->regmap;
416 spin_lock_irqsave(core->lock, flags);
419 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
422 spin_unlock_irqrestore(core->lock, flags);
424 return !!(val & core->layout->endiv_mask);
430 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
431 struct sam9x60_div *div = to_sam9x60_div(core);
436 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
441 core->characteristics;
442 struct clk_hw *parent = clk_hw_get_parent(&core->hw);
454 for (divid = 1; divid < core->layout->div_mask; divid++) {
482 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
484 return sam9x60_div_pll_compute_div(core, parent_rate, rate);
490 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
491 struct sam9x60_div *div = to_sam9x60_div(core);
501 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
502 struct sam9x60_div *div = to_sam9x60_div(core);
503 struct regmap *regmap = core->regmap;
509 spin_lock_irqsave(core->lock, irqflags);
511 core->id);
513 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
519 sam9x60_div_pll_set_div(core, div->div, 0);
522 spin_unlock_irqrestore(core->lock, irqflags);
529 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
530 struct sam9x60_div *div = to_sam9x60_div(core);
539 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
540 struct sam9x60_div *div = to_sam9x60_div(core);
543 sam9x60_div_pll_set(core);
550 struct sam9x60_pll_core core = div->core;
551 struct regmap *regmap = core.regmap;
565 spin_lock_irqsave(core.lock, irqflags);
567 core.id);
569 cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
575 sam9x60_div_pll_set_div(&core, div->div, 0);
579 spin_unlock_irqrestore(core.lock, irqflags);
644 frac->core.id = id;
645 frac->core.hw.init = &init;
646 frac->core.characteristics = characteristics;
647 frac->core.layout = layout;
648 frac->core.regmap = regmap;
649 frac->core.lock = lock;
651 spin_lock_irqsave(frac->core.lock, irqflags);
672 ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
679 spin_unlock_irqrestore(frac->core.lock, irqflags);
681 hw = &frac->core.hw;
691 spin_unlock_irqrestore(frac->core.lock, irqflags);
734 div->core.id = id;
735 div->core.hw.init = &init;
736 div->core.characteristics = characteristics;
737 div->core.layout = layout;
738 div->core.regmap = regmap;
739 div->core.lock = lock;
742 spin_lock_irqsave(div->core.lock, irqflags);
749 spin_unlock_irqrestore(div->core.lock, irqflags);
751 hw = &div->core.hw;