Lines Matching defs:periph
50 struct clk_peripheral *periph = to_clk_peripheral(hw);
52 u32 id = periph->id;
58 regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id));
65 struct clk_peripheral *periph = to_clk_peripheral(hw);
67 u32 id = periph->id;
73 regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id));
78 struct clk_peripheral *periph = to_clk_peripheral(hw);
81 u32 id = periph->id;
87 regmap_read(periph->regmap, offset, &status);
103 struct clk_peripheral *periph;
111 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
112 if (!periph)
124 periph->id = id;
125 periph->hw.init = &init;
126 periph->regmap = regmap;
128 hw = &periph->hw;
129 ret = clk_hw_register(NULL, &periph->hw);
131 kfree(periph);
138 static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph)
144 if (!periph->auto_div)
147 if (periph->range.max) {
148 parent = clk_hw_get_parent_by_index(&periph->hw, 0);
154 if (parent_rate >> shift <= periph->range.max)
159 periph->auto_div = false;
160 periph->div = shift;
163 static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph,
169 if (periph->id < PERIPHERAL_ID_MIN)
172 spin_lock_irqsave(periph->lock, flags);
173 regmap_write(periph->regmap, periph->layout->offset,
174 (periph->id & periph->layout->pid_mask));
175 regmap_update_bits(periph->regmap, periph->layout->offset,
176 periph->layout->div_mask | periph->layout->cmd |
178 field_prep(periph->layout->div_mask, periph->div) |
179 periph->layout->cmd | enable);
180 spin_unlock_irqrestore(periph->lock, flags);
187 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
189 return clk_sam9x5_peripheral_set(periph, 1);
194 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
197 if (periph->id < PERIPHERAL_ID_MIN)
200 spin_lock_irqsave(periph->lock, flags);
201 regmap_write(periph->regmap, periph->layout->offset,
202 (periph->id & periph->layout->pid_mask));
203 regmap_update_bits(periph->regmap, periph->layout->offset,
204 AT91_PMC_PCR_EN | periph->layout->cmd,
205 periph->layout->cmd);
206 spin_unlock_irqrestore(periph->lock, flags);
211 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
215 if (periph->id < PERIPHERAL_ID_MIN)
218 spin_lock_irqsave(periph->lock, flags);
219 regmap_write(periph->regmap, periph->layout->offset,
220 (periph->id & periph->layout->pid_mask));
221 regmap_read(periph->regmap, periph->layout->offset, &status);
222 spin_unlock_irqrestore(periph->lock, flags);
231 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
235 if (periph->id < PERIPHERAL_ID_MIN)
238 spin_lock_irqsave(periph->lock, flags);
239 regmap_write(periph->regmap, periph->layout->offset,
240 (periph->id & periph->layout->pid_mask));
241 regmap_read(periph->regmap, periph->layout->offset, &status);
242 spin_unlock_irqrestore(periph->lock, flags);
245 periph->div = field_get(periph->layout->div_mask, status);
246 periph->auto_div = false;
248 clk_sam9x5_peripheral_autodiv(periph);
251 return parent_rate >> periph->div;
274 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
282 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max)
289 if (periph->range.max && tmp_rate > periph->range.max)
299 if (periph->chg_pid < 0)
303 parent = clk_hw_get_parent_by_index(hw, periph->chg_pid);
322 (periph->range.max && best_rate > periph->range.max))
344 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
346 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max)
349 if (periph->range.max) {
352 if (cur_rate <= periph->range.max)
386 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
387 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) {
394 if (periph->range.max && rate > periph->range.max)
399 periph->auto_div = false;
400 periph->div = shift;
410 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
412 periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw);
419 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
421 if (periph->pms.status)
422 clk_sam9x5_peripheral_set(periph, periph->pms.status);
455 struct clk_sam9x5_peripheral *periph;
463 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
464 if (!periph)
482 periph->id = id;
483 periph->hw.init = &init;
484 periph->div = 0;
485 periph->regmap = regmap;
486 periph->lock = lock;
488 periph->auto_div = true;
489 periph->layout = layout;
490 periph->range = *range;
491 periph->chg_pid = chg_pid;
493 hw = &periph->hw;
494 ret = clk_hw_register(NULL, &periph->hw);
496 kfree(periph);
499 clk_sam9x5_peripheral_autodiv(periph);