Lines Matching refs:gck
38 static int clk_generated_set(struct clk_generated *gck, int status)
43 spin_lock_irqsave(gck->lock, flags);
44 regmap_write(gck->regmap, gck->layout->offset,
45 (gck->id & gck->layout->pid_mask));
46 regmap_update_bits(gck->regmap, gck->layout->offset,
47 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
48 gck->layout->cmd | enable,
49 field_prep(gck->layout->gckcss_mask, gck->parent_id) |
50 gck->layout->cmd |
51 FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
53 spin_unlock_irqrestore(gck->lock, flags);
60 struct clk_generated *gck = to_clk_generated(hw);
63 __func__, gck->gckdiv, gck->parent_id);
65 clk_generated_set(gck, 1);
72 struct clk_generated *gck = to_clk_generated(hw);
75 spin_lock_irqsave(gck->lock, flags);
76 regmap_write(gck->regmap, gck->layout->offset,
77 (gck->id & gck->layout->pid_mask));
78 regmap_update_bits(gck->regmap, gck->layout->offset,
79 gck->layout->cmd | AT91_PMC_PCR_GCKEN,
80 gck->layout->cmd);
81 spin_unlock_irqrestore(gck->lock, flags);
86 struct clk_generated *gck = to_clk_generated(hw);
90 spin_lock_irqsave(gck->lock, flags);
91 regmap_write(gck->regmap, gck->layout->offset,
92 (gck->id & gck->layout->pid_mask));
93 regmap_read(gck->regmap, gck->layout->offset, &status);
94 spin_unlock_irqrestore(gck->lock, flags);
103 struct clk_generated *gck = to_clk_generated(hw);
105 return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
137 struct clk_generated *gck = to_clk_generated(hw);
146 if (gck->range.max && req->rate > gck->range.max)
147 req->rate = gck->range.max;
148 if (gck->range.min && req->rate < gck->range.min)
149 req->rate = gck->range.min;
152 if (gck->chg_pid == i)
162 (gck->range.max && min_rate > gck->range.max))
183 * that the only clks able to modify gck rate are those of audio IPs.
186 if (gck->chg_pid < 0)
189 parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
212 if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
222 struct clk_generated *gck = to_clk_generated(hw);
227 if (gck->mux_table)
228 gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
230 gck->parent_id = index;
237 struct clk_generated *gck = to_clk_generated(hw);
239 return gck->parent_id;
247 struct clk_generated *gck = to_clk_generated(hw);
253 if (gck->range.max && rate > gck->range.max)
260 gck->gckdiv = div - 1;
266 struct clk_generated *gck = to_clk_generated(hw);
268 gck->pms.status = clk_generated_is_enabled(&gck->hw);
275 struct clk_generated *gck = to_clk_generated(hw);
277 if (gck->pms.status)
278 clk_generated_set(gck, gck->pms.status);
298 * @gck: Generated clock to set the startup parameters for.
303 static void clk_generated_startup(struct clk_generated *gck)
308 spin_lock_irqsave(gck->lock, flags);
309 regmap_write(gck->regmap, gck->layout->offset,
310 (gck->id & gck->layout->pid_mask));
311 regmap_read(gck->regmap, gck->layout->offset, &tmp);
312 spin_unlock_irqrestore(gck->lock, flags);
314 gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
315 gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
327 struct clk_generated *gck;
335 gck = kzalloc(sizeof(*gck), GFP_KERNEL);
336 if (!gck)
350 gck->id = id;
351 gck->hw.init = &init;
352 gck->regmap = regmap;
353 gck->lock = lock;
354 gck->range = *range;
355 gck->chg_pid = chg_pid;
356 gck->layout = layout;
357 gck->mux_table = mux_table;
359 clk_generated_startup(gck);
360 hw = &gck->hw;
361 ret = clk_hw_register(NULL, &gck->hw);
363 kfree(gck);