Lines Matching refs:parent_rate
177 * @parent_rate: PLL input refclk rate (pre-R-divider)
188 unsigned long parent_rate)
192 if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
195 c->parent_rate = parent_rate;
196 max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
199 c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
208 * @parent_rate: PLL input refclk rate (pre-R-divider)
226 unsigned long parent_rate)
240 if (parent_rate != c->parent_rate) {
241 if (__wrpll_update_parent_rate(c, parent_rate)) {
251 if (target_rate == parent_rate) {
265 ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
281 post_divr_freq = div_u64(parent_rate, r);
305 post_divr_freq = div_u64(parent_rate, best_r);
319 * @parent_rate: PLL refclk rate
322 * PLL's input reference clock rate @parent_rate (before the R
335 unsigned long parent_rate)
346 n = parent_rate * fbdiv * (c->divf + 1);