Lines Matching refs:ctx
91 struct xgene_rng_dev *ctx = from_timer(ctx, t, failure_timer);
94 disable_irq(ctx->irq);
95 ctx->failure_cnt = 0;
96 del_timer(&ctx->failure_timer);
97 enable_irq(ctx->irq);
100 static void xgene_rng_start_timer(struct xgene_rng_dev *ctx)
102 ctx->failure_timer.expires = jiffies + 120 * HZ;
103 add_timer(&ctx->failure_timer);
109 static void xgene_rng_init_fro(struct xgene_rng_dev *ctx, u32 fro_val)
111 writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
112 writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
113 writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
114 writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
117 static void xgene_rng_chk_overflow(struct xgene_rng_dev *ctx)
121 val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
128 dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val);
136 dev_err(ctx->dev, "test poker failure error 0x%08X\n", val);
142 dev_err(ctx->dev, "test long run failure error 0x%08X\n", val);
149 dev_err(ctx->dev, "test run failure error 0x%08X\n", val);
152 dev_err(ctx->dev, "noise failure error 0x%08X\n", val);
158 dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val);
164 if (++ctx->failure_cnt == 1) {
166 ctx->failure_ts = jiffies;
167 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
168 xgene_rng_init_fro(ctx, frostopped);
174 xgene_rng_start_timer(ctx);
177 if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) {
178 dev_err(ctx->dev,
183 ctx->failure_ts = jiffies;
184 ctx->failure_cnt = 1;
190 xgene_rng_start_timer(ctx);
192 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
193 xgene_rng_init_fro(ctx, frostopped);
197 writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
202 struct xgene_rng_dev *ctx = id;
205 xgene_rng_chk_overflow(ctx);
212 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
216 val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
227 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
230 for (i = 0; i < ctx->datum_size; i++)
231 data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4);
234 writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
236 return ctx->datum_size << 2;
239 static void xgene_rng_init_internal(struct xgene_rng_dev *ctx)
243 writel(0x00000000, ctx->csr_base + RNG_CONTROL);
247 writel(val, ctx->csr_base + RNG_CONFIG);
250 writel(val, ctx->csr_base + RNG_ALARMCNT);
252 xgene_rng_init_fro(ctx, 0);
261 READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
271 writel(val, ctx->csr_base + RNG_CONTROL);
276 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
278 ctx->failure_cnt = 0;
279 timer_setup(&ctx->failure_timer, xgene_rng_expired_timer, 0);
281 ctx->revision = readl(ctx->csr_base + RNG_EIP_REV);
283 dev_dbg(ctx->dev, "Rev %d.%d.%d\n",
284 MAJOR_HW_REV_RD(ctx->revision),
285 MINOR_HW_REV_RD(ctx->revision),
286 HW_PATCH_LEVEL_RD(ctx->revision));
288 dev_dbg(ctx->dev, "Options 0x%08X",
289 readl(ctx->csr_base + RNG_OPTIONS));
291 xgene_rng_init_internal(ctx);
293 ctx->datum_size = RNG_MAX_DATUM;
315 struct xgene_rng_dev *ctx;
319 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
320 if (!ctx)
323 ctx->dev = &pdev->dev;
324 platform_set_drvdata(pdev, ctx);
326 ctx->csr_base = devm_platform_ioremap_resource(pdev, 0);
327 if (IS_ERR(ctx->csr_base))
328 return PTR_ERR(ctx->csr_base);
333 ctx->irq = rc;
336 ctx->csr_base, ctx->irq);
338 rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0,
339 dev_name(&pdev->dev), ctx);
348 xgene_rng_func.priv = (unsigned long) ctx;