Lines Matching defs:intel_private
90 } intel_private;
92 #define INTEL_GTT_GEN intel_private.driver->gen
93 #define IS_G33 intel_private.driver->is_g33
94 #define IS_PINEVIEW intel_private.driver->is_pineview
95 #define IS_IRONLAKE intel_private.driver->is_ironlake
96 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
114 if (!dma_map_sg(&intel_private.pcidev->dev, st->sgl, st->nents,
130 dma_unmap_sg(&intel_private.pcidev->dev, sg_list, num_sg,
183 intel_private.i81x_gtt_table = gtt_table;
185 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
187 intel_private.registers = ioremap(reg_addr, KB(64));
188 if (!intel_private.registers)
192 intel_private.registers+I810_PGETBL_CTL);
194 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
196 if ((readl(intel_private.registers+I810_DRAM_CTL)
198 dev_info(&intel_private.pcidev->dev,
200 intel_private.num_dcache_entries = 1024;
208 writel(0, intel_private.registers+I810_PGETBL_CTL);
209 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
219 > intel_private.num_dcache_entries)
227 intel_private.driver->write_entry(addr,
305 if (intel_private.needs_dmar) {
306 dma_addr = dma_map_page(&intel_private.pcidev->dev, page, 0,
308 if (dma_mapping_error(&intel_private.pcidev->dev, dma_addr)) {
313 intel_private.scratch_page_dma = dma_addr;
315 intel_private.scratch_page_dma = page_to_phys(page);
317 intel_private.scratch_page = page;
336 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
350 pci_read_config_word(intel_private.bridge_dev,
353 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
354 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
366 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
423 dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s memory\n",
426 dev_info(&intel_private.bridge_dev->dev,
439 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
441 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
444 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
447 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
456 pci_read_config_word(intel_private.bridge_dev,
475 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
498 dev_info(&intel_private.pcidev->dev,
514 return intel_private.gtt_mappable_entries;
525 pci_read_config_dword(intel_private.bridge_dev,
536 pci_read_config_word(intel_private.bridge_dev,
545 aperture_size = pci_resource_len(intel_private.pcidev, 2);
553 set_pages_wb(intel_private.scratch_page, 1);
554 if (intel_private.needs_dmar)
555 dma_unmap_page(&intel_private.pcidev->dev,
556 intel_private.scratch_page_dma, PAGE_SIZE,
558 __free_page(intel_private.scratch_page);
563 intel_private.driver->cleanup();
565 iounmap(intel_private.gtt);
566 iounmap(intel_private.registers);
576 const unsigned short gpu_devid = intel_private.pcidev->device;
584 device_iommu_mapped(&intel_private.pcidev->dev));
607 ret = intel_private.driver->setup();
611 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
612 intel_private.gtt_total_entries = intel_gtt_total_entries();
615 intel_private.PGETBL_save =
616 readl(intel_private.registers+I810_PGETBL_CTL)
620 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
622 dev_info(&intel_private.bridge_dev->dev,
624 intel_private.gtt_total_entries * 4,
625 intel_private.gtt_mappable_entries * 4);
627 gtt_map_size = intel_private.gtt_total_entries * 4;
629 intel_private.gtt = NULL;
631 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
633 if (intel_private.gtt == NULL)
634 intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
636 if (intel_private.gtt == NULL) {
637 intel_private.driver->cleanup();
638 iounmap(intel_private.registers);
646 intel_private.stolen_size = intel_gtt_stolen_size();
648 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
661 intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
680 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
722 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
723 intel_private.registers+I830_HIC);
725 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
741 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
751 pci_read_config_word(intel_private.bridge_dev,
754 pci_write_config_word(intel_private.bridge_dev,
757 pci_read_config_word(intel_private.bridge_dev,
760 dev_err(&intel_private.pcidev->dev,
771 writel(0, intel_private.registers+GFX_FLSH_CNTL);
773 reg = intel_private.registers+I810_PGETBL_CTL;
774 writel(intel_private.PGETBL_save, reg);
776 dev_err(&intel_private.pcidev->dev,
778 readl(reg), intel_private.PGETBL_save);
783 writel(0, intel_private.registers+GFX_FLSH_CNTL);
793 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
795 intel_private.registers = ioremap(reg_addr, KB(64));
796 if (!intel_private.registers)
799 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
824 intel_private.clear_fake_agp = true;
825 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
848 intel_private.driver->write_entry(addr, pg, flags);
849 readl(intel_private.gtt + pg);
850 if (intel_private.driver->chipset_flush)
851 intel_private.driver->chipset_flush();
871 intel_private.driver->write_entry(addr, j, flags);
875 readl(intel_private.gtt + j - 1);
876 if (intel_private.driver->chipset_flush)
877 intel_private.driver->chipset_flush();
891 intel_private.driver->write_entry(addr,
902 if (intel_private.clear_fake_agp) {
903 int start = intel_private.stolen_size / PAGE_SIZE;
904 int end = intel_private.gtt_mappable_entries;
906 intel_private.clear_fake_agp = false;
915 if (pg_start + mem->page_count > intel_private.gtt_total_entries)
921 if (!intel_private.driver->check_flags(type))
927 if (intel_private.needs_dmar) {
954 intel_private.driver->write_entry(intel_private.scratch_page_dma,
970 if (intel_private.needs_dmar) {
985 if (pg_count != intel_private.num_dcache_entries)
1008 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1010 pcibios_align_resource, intel_private.bridge_dev);
1020 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1023 intel_private.resource_valid = 1;
1024 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1028 intel_private.resource_valid = 1;
1029 intel_private.ifp_resource.start = temp;
1030 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1031 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1034 intel_private.resource_valid = 0;
1043 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1044 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1050 intel_private.resource_valid = 1;
1051 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1052 upper_32_bits(intel_private.ifp_resource.start));
1053 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1060 intel_private.resource_valid = 1;
1061 intel_private.ifp_resource.start = l64;
1062 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1063 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1066 intel_private.resource_valid = 0;
1073 if (intel_private.ifp_resource.start)
1080 intel_private.ifp_resource.name = "Intel Flush Page";
1081 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1090 if (intel_private.ifp_resource.start)
1091 intel_private.i9xx_flush_page = ioremap(intel_private.ifp_resource.start, PAGE_SIZE);
1092 if (!intel_private.i9xx_flush_page)
1093 dev_err(&intel_private.pcidev->dev,
1099 if (intel_private.i9xx_flush_page)
1100 iounmap(intel_private.i9xx_flush_page);
1101 if (intel_private.resource_valid)
1102 release_resource(&intel_private.ifp_resource);
1103 intel_private.ifp_resource.start = 0;
1104 intel_private.resource_valid = 0;
1110 if (intel_private.i9xx_flush_page)
1111 writel(1, intel_private.i9xx_flush_page);
1126 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
1134 reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1136 intel_private.registers = ioremap(reg_addr, size);
1137 if (!intel_private.registers)
1142 intel_private.gtt_phys_addr =
1143 pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1146 intel_private.gtt_phys_addr = reg_addr + MB(2);
1149 intel_private.gtt_phys_addr = reg_addr + KB(512);
1357 intel_private.pcidev = gmch_device;
1370 intel_private.pcidev = pci_dev_get(gpu_pdev);
1371 intel_private.driver =
1377 intel_private.driver =
1383 if (!intel_private.driver)
1392 bridge->dev_private_data = &intel_private;
1403 if (intel_private.refcount++)
1406 intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1411 mask = intel_private.driver->dma_mask_size;
1412 if (dma_set_mask(&intel_private.pcidev->dev, DMA_BIT_MASK(mask)))
1413 dev_err(&intel_private.pcidev->dev,
1417 dma_set_coherent_mask(&intel_private.pcidev->dev,
1435 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1436 *mappable_base = intel_private.gma_bus_addr;
1437 *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1443 if (intel_private.driver->chipset_flush)
1444 intel_private.driver->chipset_flush();
1450 if (--intel_private.refcount)
1453 if (intel_private.scratch_page)
1455 if (intel_private.pcidev)
1456 pci_dev_put(intel_private.pcidev);
1457 if (intel_private.bridge_dev)
1458 pci_dev_put(intel_private.bridge_dev);
1459 intel_private.driver = NULL;