Lines Matching defs:temp
107 u8 temp;
111 pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
112 i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
126 pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
129 if (temp & I460_SRAM_IO_DISABLE) {
136 if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) {
142 if (temp & I460_BAPBASE_ENABLE)
159 if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
181 u8 temp;
183 pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
185 ((temp & ~I460_AGPSIZ_MASK) | size_value));
204 } temp;
209 temp.large = 0;
219 pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
220 pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));
223 agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);
245 void *temp;
250 temp = agp_bridge->current_size;
251 page_order = A_SIZE_8(temp)->page_order;
252 num_entries = A_SIZE_8(temp)->num_entries;
274 void *temp;
276 temp = agp_bridge->current_size;
278 num_entries = A_SIZE_8(temp)->num_entries;
298 void *temp;
308 temp = agp_bridge->current_size;
309 num_entries = A_SIZE_8(temp)->num_entries;
405 void *temp;
410 temp = agp_bridge->current_size;
411 num_entries = A_SIZE_8(temp)->num_entries;
466 void *temp;
468 temp = agp_bridge->current_size;
469 num_entries = A_SIZE_8(temp)->num_entries;