Lines Matching defs:mhi_cntrl
111 enum mhi_pm_state __must_check mhi_tryset_pm_state(struct mhi_controller *mhi_cntrl,
114 unsigned long cur_state = mhi_cntrl->pm_state;
126 mhi_cntrl->pm_state = state;
127 return mhi_cntrl->pm_state;
130 void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state)
132 struct device *dev = &mhi_cntrl->mhi_dev->dev;
136 ret = mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
139 ret = mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
149 static void mhi_toggle_dev_wake_nop(struct mhi_controller *mhi_cntrl)
153 static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl)
155 mhi_cntrl->wake_get(mhi_cntrl, false);
156 mhi_cntrl->wake_put(mhi_cntrl, true);
160 int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)
164 struct device *dev = &mhi_cntrl->mhi_dev->dev;
169 if (MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
175 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
182 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS,
190 write_lock_irq(&mhi_cntrl->pm_lock);
191 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
192 mhi_cntrl->dev_state = MHI_STATE_READY;
193 write_unlock_irq(&mhi_cntrl->pm_lock);
202 read_lock_bh(&mhi_cntrl->pm_lock);
203 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
209 ret = mhi_init_mmio(mhi_cntrl);
216 mhi_event = mhi_cntrl->mhi_event;
217 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
236 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
237 read_unlock_bh(&mhi_cntrl->pm_lock);
242 read_unlock_bh(&mhi_cntrl->pm_lock);
247 int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl)
251 struct device *dev = &mhi_cntrl->mhi_dev->dev;
254 write_lock_irq(&mhi_cntrl->pm_lock);
255 mhi_cntrl->dev_state = MHI_STATE_M0;
256 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M0);
257 write_unlock_irq(&mhi_cntrl->pm_lock);
262 mhi_cntrl->M0++;
265 read_lock_bh(&mhi_cntrl->pm_lock);
266 mhi_cntrl->wake_get(mhi_cntrl, true);
269 if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) {
270 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
272 &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING];
274 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
286 mhi_ring_cmd_db(mhi_cntrl, mhi_cmd);
291 mhi_chan = mhi_cntrl->mhi_chan;
292 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
306 mhi_ring_chan_db(mhi_cntrl, mhi_chan);
310 mhi_cntrl->wake_put(mhi_cntrl, false);
311 read_unlock_bh(&mhi_cntrl->pm_lock);
312 wake_up_all(&mhi_cntrl->state_event);
322 void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl)
325 struct device *dev = &mhi_cntrl->mhi_dev->dev;
327 write_lock_irq(&mhi_cntrl->pm_lock);
328 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M2);
330 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M2);
331 mhi_cntrl->dev_state = MHI_STATE_M2;
333 write_unlock_irq(&mhi_cntrl->pm_lock);
335 mhi_cntrl->M2++;
336 wake_up_all(&mhi_cntrl->state_event);
339 if (unlikely(atomic_read(&mhi_cntrl->pending_pkts) ||
340 atomic_read(&mhi_cntrl->dev_wake))) {
343 atomic_read(&mhi_cntrl->pending_pkts),
344 atomic_read(&mhi_cntrl->dev_wake));
345 read_lock_bh(&mhi_cntrl->pm_lock);
346 mhi_cntrl->wake_get(mhi_cntrl, true);
347 mhi_cntrl->wake_put(mhi_cntrl, true);
348 read_unlock_bh(&mhi_cntrl->pm_lock);
350 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_IDLE);
353 write_unlock_irq(&mhi_cntrl->pm_lock);
358 int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl)
361 struct device *dev = &mhi_cntrl->mhi_dev->dev;
363 write_lock_irq(&mhi_cntrl->pm_lock);
364 mhi_cntrl->dev_state = MHI_STATE_M3;
365 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3);
366 write_unlock_irq(&mhi_cntrl->pm_lock);
372 mhi_cntrl->M3++;
373 wake_up_all(&mhi_cntrl->state_event);
379 static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl)
382 struct device *dev = &mhi_cntrl->mhi_dev->dev;
383 enum mhi_ee_type ee = MHI_EE_MAX, current_ee = mhi_cntrl->ee;
388 write_lock_irq(&mhi_cntrl->pm_lock);
389 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
390 ee = mhi_get_exec_env(mhi_cntrl);
393 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
394 write_unlock_irq(&mhi_cntrl->pm_lock);
395 wake_up_all(&mhi_cntrl->state_event);
398 mhi_cntrl->ee = ee;
399 write_unlock_irq(&mhi_cntrl->pm_lock);
401 wake_up_all(&mhi_cntrl->state_event);
403 device_for_each_child(&mhi_cntrl->mhi_dev->dev, ¤t_ee,
405 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_MISSION_MODE);
408 ret = __mhi_device_get_sync(mhi_cntrl);
412 read_lock_bh(&mhi_cntrl->pm_lock);
414 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
420 mhi_event = mhi_cntrl->mhi_event;
421 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
433 if (MHI_DB_ACCESS_VALID(mhi_cntrl))
438 read_unlock_bh(&mhi_cntrl->pm_lock);
444 mhi_create_devices(mhi_cntrl);
446 read_lock_bh(&mhi_cntrl->pm_lock);
449 mhi_cntrl->wake_put(mhi_cntrl, false);
450 read_unlock_bh(&mhi_cntrl->pm_lock);
456 static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)
463 struct device *dev = &mhi_cntrl->mhi_dev->dev;
467 to_mhi_pm_state_str(mhi_cntrl->pm_state));
469 mutex_lock(&mhi_cntrl->pm_mutex);
472 if (!MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
474 if (mhi_cntrl->rddm_image && mhi_get_exec_env(mhi_cntrl) == MHI_EE_RDDM)
478 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
481 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
490 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
492 if (!MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
494 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs,
505 mhi_event = mhi_cntrl->mhi_event;
506 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
509 disable_irq(mhi_cntrl->irq[mhi_event->irq]);
514 mutex_unlock(&mhi_cntrl->pm_mutex);
516 wake_up_all(&mhi_cntrl->state_event);
519 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
521 mutex_lock(&mhi_cntrl->pm_mutex);
523 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
524 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
528 mhi_cmd = mhi_cntrl->mhi_cmd;
529 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
539 mhi_event = mhi_cntrl->mhi_event;
540 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
541 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
556 write_lock_irq(&mhi_cntrl->pm_lock);
557 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_DISABLE);
558 write_unlock_irq(&mhi_cntrl->pm_lock);
565 to_mhi_pm_state_str(mhi_cntrl->pm_state),
566 mhi_state_str(mhi_cntrl->dev_state));
568 mutex_unlock(&mhi_cntrl->pm_mutex);
572 static void mhi_pm_sys_error_transition(struct mhi_controller *mhi_cntrl)
580 struct device *dev = &mhi_cntrl->mhi_dev->dev;
584 to_mhi_pm_state_str(mhi_cntrl->pm_state),
588 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR);
590 mutex_lock(&mhi_cntrl->pm_mutex);
591 write_lock_irq(&mhi_cntrl->pm_lock);
592 prev_state = mhi_cntrl->pm_state;
593 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_PROCESS);
594 write_unlock_irq(&mhi_cntrl->pm_lock);
603 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
604 mhi_cntrl->dev_state = MHI_STATE_RESET;
607 wake_up_all(&mhi_cntrl->state_event);
612 unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms);
615 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
618 ret = wait_event_timeout(mhi_cntrl->state_event,
619 mhi_read_reg_field(mhi_cntrl,
620 mhi_cntrl->regs,
634 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
639 mhi_event = mhi_cntrl->mhi_event;
640 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
647 mutex_unlock(&mhi_cntrl->pm_mutex);
649 wake_up_all(&mhi_cntrl->state_event);
652 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
654 mutex_lock(&mhi_cntrl->pm_mutex);
656 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
657 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
661 mhi_cmd = mhi_cntrl->mhi_cmd;
662 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
672 mhi_event = mhi_cntrl->mhi_event;
673 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
674 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
689 if (MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
690 write_lock_irq(&mhi_cntrl->pm_lock);
691 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
692 write_unlock_irq(&mhi_cntrl->pm_lock);
704 mhi_queue_state_transition(mhi_cntrl, next_state);
708 to_mhi_pm_state_str(mhi_cntrl->pm_state),
709 mhi_state_str(mhi_cntrl->dev_state));
711 mutex_unlock(&mhi_cntrl->pm_mutex);
715 int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl,
725 spin_lock_irqsave(&mhi_cntrl->transition_lock, flags);
726 list_add_tail(&item->node, &mhi_cntrl->transition_list);
727 spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags);
729 queue_work(mhi_cntrl->hiprio_wq, &mhi_cntrl->st_worker);
735 void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl)
737 struct device *dev = &mhi_cntrl->mhi_dev->dev;
740 if (mhi_cntrl->rddm_image) {
745 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR);
753 struct mhi_controller *mhi_cntrl = container_of(work,
756 struct device *dev = &mhi_cntrl->mhi_dev->dev;
758 spin_lock_irq(&mhi_cntrl->transition_lock);
759 list_splice_tail_init(&mhi_cntrl->transition_list, &head);
760 spin_unlock_irq(&mhi_cntrl->transition_lock);
769 write_lock_irq(&mhi_cntrl->pm_lock);
770 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
771 mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
772 write_unlock_irq(&mhi_cntrl->pm_lock);
773 mhi_fw_load_handler(mhi_cntrl);
776 write_lock_irq(&mhi_cntrl->pm_lock);
777 mhi_cntrl->ee = MHI_EE_SBL;
778 write_unlock_irq(&mhi_cntrl->pm_lock);
784 mhi_create_devices(mhi_cntrl);
785 if (mhi_cntrl->fbc_download)
786 mhi_download_amss_image(mhi_cntrl);
789 mhi_pm_mission_mode_transition(mhi_cntrl);
792 write_lock_irq(&mhi_cntrl->pm_lock);
793 mhi_cntrl->ee = MHI_EE_FP;
794 write_unlock_irq(&mhi_cntrl->pm_lock);
795 mhi_create_devices(mhi_cntrl);
798 mhi_ready_state_transition(mhi_cntrl);
801 mhi_pm_sys_error_transition(mhi_cntrl);
804 mhi_pm_disable_transition(mhi_cntrl);
813 int mhi_pm_suspend(struct mhi_controller *mhi_cntrl)
816 struct device *dev = &mhi_cntrl->mhi_dev->dev;
820 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
823 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
827 if (atomic_read(&mhi_cntrl->dev_wake) ||
828 atomic_read(&mhi_cntrl->pending_pkts))
832 read_lock_bh(&mhi_cntrl->pm_lock);
833 mhi_cntrl->wake_get(mhi_cntrl, false);
834 read_unlock_bh(&mhi_cntrl->pm_lock);
836 ret = wait_event_timeout(mhi_cntrl->state_event,
837 mhi_cntrl->dev_state == MHI_STATE_M0 ||
838 mhi_cntrl->dev_state == MHI_STATE_M1 ||
839 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
840 msecs_to_jiffies(mhi_cntrl->timeout_ms));
842 read_lock_bh(&mhi_cntrl->pm_lock);
843 mhi_cntrl->wake_put(mhi_cntrl, false);
844 read_unlock_bh(&mhi_cntrl->pm_lock);
846 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
852 write_lock_irq(&mhi_cntrl->pm_lock);
854 if (atomic_read(&mhi_cntrl->dev_wake) ||
855 atomic_read(&mhi_cntrl->pending_pkts)) {
856 write_unlock_irq(&mhi_cntrl->pm_lock);
861 new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER);
863 write_unlock_irq(&mhi_cntrl->pm_lock);
867 to_mhi_pm_state_str(mhi_cntrl->pm_state));
872 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
873 write_unlock_irq(&mhi_cntrl->pm_lock);
876 ret = wait_event_timeout(mhi_cntrl->state_event,
877 mhi_cntrl->dev_state == MHI_STATE_M3 ||
878 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
879 msecs_to_jiffies(mhi_cntrl->timeout_ms));
881 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
884 mhi_state_str(mhi_cntrl->dev_state),
885 to_mhi_pm_state_str(mhi_cntrl->pm_state));
890 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
901 static int __mhi_pm_resume(struct mhi_controller *mhi_cntrl, bool force)
904 struct device *dev = &mhi_cntrl->mhi_dev->dev;
909 to_mhi_pm_state_str(mhi_cntrl->pm_state),
910 mhi_state_str(mhi_cntrl->dev_state));
912 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
915 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
918 if (mhi_get_mhi_state(mhi_cntrl) != MHI_STATE_M3) {
920 mhi_state_str(mhi_get_mhi_state(mhi_cntrl)));
926 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
933 write_lock_irq(&mhi_cntrl->pm_lock);
934 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT);
936 write_unlock_irq(&mhi_cntrl->pm_lock);
940 to_mhi_pm_state_str(mhi_cntrl->pm_state));
945 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
946 write_unlock_irq(&mhi_cntrl->pm_lock);
948 ret = wait_event_timeout(mhi_cntrl->state_event,
949 mhi_cntrl->dev_state == MHI_STATE_M0 ||
950 mhi_cntrl->dev_state == MHI_STATE_M2 ||
951 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
952 msecs_to_jiffies(mhi_cntrl->timeout_ms));
954 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
957 mhi_state_str(mhi_cntrl->dev_state),
958 to_mhi_pm_state_str(mhi_cntrl->pm_state));
965 int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
967 return __mhi_pm_resume(mhi_cntrl, false);
971 int mhi_pm_resume_force(struct mhi_controller *mhi_cntrl)
973 return __mhi_pm_resume(mhi_cntrl, true);
977 int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl)
982 read_lock_bh(&mhi_cntrl->pm_lock);
983 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
984 read_unlock_bh(&mhi_cntrl->pm_lock);
987 mhi_cntrl->wake_get(mhi_cntrl, true);
988 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
989 mhi_trigger_resume(mhi_cntrl);
990 read_unlock_bh(&mhi_cntrl->pm_lock);
992 ret = wait_event_timeout(mhi_cntrl->state_event,
993 mhi_cntrl->pm_state == MHI_PM_M0 ||
994 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
995 msecs_to_jiffies(mhi_cntrl->timeout_ms));
997 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
998 read_lock_bh(&mhi_cntrl->pm_lock);
999 mhi_cntrl->wake_put(mhi_cntrl, false);
1000 read_unlock_bh(&mhi_cntrl->pm_lock);
1008 static void mhi_assert_dev_wake(struct mhi_controller *mhi_cntrl, bool force)
1017 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1018 atomic_inc(&mhi_cntrl->dev_wake);
1019 if (MHI_WAKE_DB_FORCE_SET_VALID(mhi_cntrl->pm_state) &&
1020 !mhi_cntrl->wake_set) {
1021 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
1022 mhi_cntrl->wake_set = true;
1024 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1030 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, 1, 0)))
1033 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1034 if ((atomic_inc_return(&mhi_cntrl->dev_wake) == 1) &&
1035 MHI_WAKE_DB_SET_VALID(mhi_cntrl->pm_state) &&
1036 !mhi_cntrl->wake_set) {
1037 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
1038 mhi_cntrl->wake_set = true;
1040 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1045 static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl,
1054 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, -1, 1)))
1057 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1058 if ((atomic_dec_return(&mhi_cntrl->dev_wake) == 0) &&
1059 MHI_WAKE_DB_CLEAR_VALID(mhi_cntrl->pm_state) && !override &&
1060 mhi_cntrl->wake_set) {
1061 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 0);
1062 mhi_cntrl->wake_set = false;
1064 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1067 int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
1069 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
1073 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1080 if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put ||
1081 !mhi_cntrl->wake_toggle) {
1082 mhi_cntrl->wake_get = mhi_assert_dev_wake;
1083 mhi_cntrl->wake_put = mhi_deassert_dev_wake;
1084 mhi_cntrl->wake_toggle = (mhi_cntrl->db_access & MHI_PM_M2) ?
1088 mutex_lock(&mhi_cntrl->pm_mutex);
1089 mhi_cntrl->pm_state = MHI_PM_DISABLE;
1092 write_lock_irq(&mhi_cntrl->pm_lock);
1093 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1094 mhi_cntrl->pm_state = MHI_PM_POR;
1095 mhi_cntrl->ee = MHI_EE_MAX;
1096 current_ee = mhi_get_exec_env(mhi_cntrl);
1097 write_unlock_irq(&mhi_cntrl->pm_lock);
1107 state = mhi_get_mhi_state(mhi_cntrl);
1112 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
1113 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
1124 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1128 enable_irq(mhi_cntrl->irq[0]);
1130 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
1134 enable_irq(mhi_cntrl->irq[mhi_event->irq]);
1141 mhi_queue_state_transition(mhi_cntrl, next_state);
1143 mutex_unlock(&mhi_cntrl->pm_mutex);
1150 mhi_cntrl->pm_state = MHI_PM_DISABLE;
1151 mutex_unlock(&mhi_cntrl->pm_mutex);
1157 void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
1160 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1162 mutex_lock(&mhi_cntrl->pm_mutex);
1163 write_lock_irq(&mhi_cntrl->pm_lock);
1164 cur_state = mhi_cntrl->pm_state;
1166 write_unlock_irq(&mhi_cntrl->pm_lock);
1167 mutex_unlock(&mhi_cntrl->pm_mutex);
1175 cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state);
1179 to_mhi_pm_state_str(mhi_cntrl->pm_state));
1181 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
1185 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
1186 mhi_cntrl->dev_state = MHI_STATE_RESET;
1188 wake_up_all(&mhi_cntrl->state_event);
1190 write_unlock_irq(&mhi_cntrl->pm_lock);
1191 mutex_unlock(&mhi_cntrl->pm_mutex);
1193 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE);
1196 flush_work(&mhi_cntrl->st_worker);
1198 disable_irq(mhi_cntrl->irq[0]);
1202 int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
1204 int ret = mhi_async_power_up(mhi_cntrl);
1209 wait_event_timeout(mhi_cntrl->state_event,
1210 MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
1211 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
1212 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1214 ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
1216 mhi_power_down(mhi_cntrl, false);
1222 int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl)
1224 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1228 if (mhi_cntrl->ee == MHI_EE_RDDM)
1232 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
1235 ret = wait_event_timeout(mhi_cntrl->state_event,
1236 mhi_cntrl->ee == MHI_EE_RDDM,
1237 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1246 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1249 read_lock_bh(&mhi_cntrl->pm_lock);
1250 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1251 mhi_trigger_resume(mhi_cntrl);
1253 mhi_cntrl->wake_get(mhi_cntrl, true);
1254 read_unlock_bh(&mhi_cntrl->pm_lock);
1260 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1263 ret = __mhi_device_get_sync(mhi_cntrl);
1273 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1276 read_lock_bh(&mhi_cntrl->pm_lock);
1277 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1278 mhi_trigger_resume(mhi_cntrl);
1280 mhi_cntrl->wake_put(mhi_cntrl, false);
1281 read_unlock_bh(&mhi_cntrl->pm_lock);