Lines Matching defs:mhi_cntrl
22 int mhi_rddm_prepare(struct mhi_controller *mhi_cntrl,
27 void __iomem *base = mhi_cntrl->bhie;
28 struct device *dev = &mhi_cntrl->mhi_dev->dev;
40 mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS,
43 mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS,
46 mhi_write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len);
49 ret = mhi_write_reg_field(mhi_cntrl, base, BHIE_RXVECDB_OFFS,
63 static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl)
69 u32 retry = (mhi_cntrl->timeout_ms * 1000) / delayus;
72 void __iomem *base = mhi_cntrl->bhie;
73 struct device *dev = &mhi_cntrl->mhi_dev->dev;
76 to_mhi_pm_state_str(mhi_cntrl->pm_state),
77 mhi_state_str(mhi_cntrl->dev_state),
78 TO_MHI_EXEC_STR(mhi_cntrl->ee));
90 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
100 ee = mhi_get_exec_env(mhi_cntrl);
106 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
110 ee = mhi_get_exec_env(mhi_cntrl);
121 mhi_soc_reset(mhi_cntrl);
125 ee = mhi_get_exec_env(mhi_cntrl);
133 ret = mhi_read_reg_field(mhi_cntrl, base, BHIE_RXVECSTATUS_OFFS,
144 ee = mhi_get_exec_env(mhi_cntrl);
145 ret = mhi_read_reg(mhi_cntrl, base, BHIE_RXVECSTATUS_OFFS, &rx_status);
157 int mhi_download_rddm_image(struct mhi_controller *mhi_cntrl, bool in_panic)
159 void __iomem *base = mhi_cntrl->bhie;
160 struct device *dev = &mhi_cntrl->mhi_dev->dev;
164 return __mhi_download_rddm_in_panic(mhi_cntrl);
169 wait_event_timeout(mhi_cntrl->state_event,
170 mhi_read_reg_field(mhi_cntrl, base,
174 msecs_to_jiffies(mhi_cntrl->timeout_ms));
180 static int mhi_fw_load_bhie(struct mhi_controller *mhi_cntrl,
183 void __iomem *base = mhi_cntrl->bhie;
184 struct device *dev = &mhi_cntrl->mhi_dev->dev;
185 rwlock_t *pm_lock = &mhi_cntrl->pm_lock;
190 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
198 mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS,
201 mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS,
204 mhi_write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len);
206 ret = mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS,
214 ret = wait_event_timeout(mhi_cntrl->state_event,
215 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) ||
216 mhi_read_reg_field(mhi_cntrl, base,
220 msecs_to_jiffies(mhi_cntrl->timeout_ms));
221 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) ||
228 static int mhi_fw_load_bhi(struct mhi_controller *mhi_cntrl,
234 void __iomem *base = mhi_cntrl->bhi;
235 rwlock_t *pm_lock = &mhi_cntrl->pm_lock;
236 struct device *dev = &mhi_cntrl->mhi_dev->dev;
249 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
257 mhi_write_reg(mhi_cntrl, base, BHI_STATUS, 0);
258 mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH,
260 mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW,
262 mhi_write_reg(mhi_cntrl, base, BHI_IMGSIZE, size);
263 mhi_write_reg(mhi_cntrl, base, BHI_IMGTXDB, session_id);
267 ret = wait_event_timeout(mhi_cntrl->state_event,
268 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) ||
269 mhi_read_reg_field(mhi_cntrl, base, BHI_STATUS,
271 msecs_to_jiffies(mhi_cntrl->timeout_ms));
272 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
278 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
280 ret = mhi_read_reg(mhi_cntrl, base,
299 void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl,
306 dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len,
313 int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl,
317 size_t seg_size = mhi_cntrl->seg_len;
343 mhi_buf->buf = dma_alloc_coherent(mhi_cntrl->cntrl_dev,
358 dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len,
367 static void mhi_firmware_copy(struct mhi_controller *mhi_cntrl,
388 void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl)
391 struct device *dev = &mhi_cntrl->mhi_dev->dev;
400 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
406 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_SERIALNU,
407 &mhi_cntrl->serial_number);
411 for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++) {
412 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_OEMPKHASH(i),
413 &mhi_cntrl->oem_pk_hash[i]);
421 if (!MHI_FW_LOAD_CAPABLE(mhi_cntrl->ee))
424 fw_name = (mhi_cntrl->ee == MHI_EE_EDL) ?
425 mhi_cntrl->edl_image : mhi_cntrl->fw_image;
428 if (!fw_name && mhi_cntrl->fbc_download &&
429 mhi_cntrl->fw_data && mhi_cntrl->fw_sz) {
430 if (!mhi_cntrl->sbl_size) {
435 size = mhi_cntrl->sbl_size;
436 fw_data = mhi_cntrl->fw_data;
437 fw_sz = mhi_cntrl->fw_sz;
441 if (!fw_name || (mhi_cntrl->fbc_download && (!mhi_cntrl->sbl_size ||
442 !mhi_cntrl->seg_len))) {
454 size = (mhi_cntrl->fbc_download) ? mhi_cntrl->sbl_size : firmware->size;
464 buf = dma_alloc_coherent(mhi_cntrl->cntrl_dev, size, &dma_addr,
473 ret = mhi_fw_load_bhi(mhi_cntrl, dma_addr, size);
474 dma_free_coherent(mhi_cntrl->cntrl_dev, size, buf, dma_addr);
484 if (fw_name && fw_name == mhi_cntrl->edl_image) {
489 write_lock_irq(&mhi_cntrl->pm_lock);
490 mhi_cntrl->dev_state = MHI_STATE_RESET;
491 write_unlock_irq(&mhi_cntrl->pm_lock);
497 if (mhi_cntrl->fbc_download) {
498 ret = mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->fbc_image, fw_sz);
505 mhi_firmware_copy(mhi_cntrl, fw_data, fw_sz, mhi_cntrl->fbc_image);
512 ret = mhi_ready_state_transition(mhi_cntrl);
522 if (mhi_cntrl->fbc_download) {
523 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
524 mhi_cntrl->fbc_image = NULL;
528 write_lock_irq(&mhi_cntrl->pm_lock);
529 new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_FW_DL_ERR);
530 write_unlock_irq(&mhi_cntrl->pm_lock);
532 wake_up_all(&mhi_cntrl->state_event);
535 int mhi_download_amss_image(struct mhi_controller *mhi_cntrl)
537 struct image_info *image_info = mhi_cntrl->fbc_image;
538 struct device *dev = &mhi_cntrl->mhi_dev->dev;
545 ret = mhi_fw_load_bhie(mhi_cntrl,
550 write_lock_irq(&mhi_cntrl->pm_lock);
551 new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_FW_DL_ERR);
552 write_unlock_irq(&mhi_cntrl->pm_lock);
554 wake_up_all(&mhi_cntrl->state_event);