Lines Matching defs:val
2293 u8 val = 0x00;
2297 skb = __hci_cmd_sync(hdev, 0xfc3b, 1, &val, HCI_INIT_TIMEOUT);
2896 static int btusb_mtk_uhw_reg_write(struct btusb_data *data, u32 reg, u32 val)
2906 put_unaligned_le32(val, buf);
2924 static int btusb_mtk_uhw_reg_read(struct btusb_data *data, u32 reg, u32 *val)
2944 *val = get_unaligned_le32(buf);
2945 bt_dev_dbg(hdev, "reg=%x, value=0x%08x", reg, *val);
2953 static int btusb_mtk_reg_read(struct btusb_data *data, u32 reg, u32 *val)
2970 *val = get_unaligned_le32(buf);
2986 u32 val = 0;
2988 btusb_mtk_uhw_reg_read(data, MTK_BT_MISC, &val);
2990 return val & MTK_BT_RST_DONE;
2997 u32 val;
3015 btusb_mtk_uhw_reg_read(data, MTK_BT_RESET_REG_CONNV3, &val);
3016 val |= (1 << 5);
3017 btusb_mtk_uhw_reg_write(data, MTK_BT_RESET_REG_CONNV3, val);
3018 btusb_mtk_uhw_reg_read(data, MTK_BT_RESET_REG_CONNV3, &val);
3019 val &= 0xFFFF00FF;
3020 val |= (1 << 13);
3021 btusb_mtk_uhw_reg_write(data, MTK_BT_RESET_REG_CONNV3, val);
3023 btusb_mtk_uhw_reg_read(data, MTK_BT_RESET_REG_CONNV3, &val);
3024 val |= (1 << 0);
3025 btusb_mtk_uhw_reg_write(data, MTK_BT_RESET_REG_CONNV3, val);
3027 btusb_mtk_uhw_reg_read(data, MTK_UDMA_INT_STA_BT, &val);
3029 btusb_mtk_uhw_reg_read(data, MTK_UDMA_INT_STA_BT1, &val);
3035 btusb_mtk_uhw_reg_read(data, MTK_BT_WDT_STATUS, &val);
3040 btusb_mtk_uhw_reg_read(data, MTK_UDMA_INT_STA_BT, &val);
3042 btusb_mtk_uhw_reg_read(data, MTK_UDMA_INT_STA_BT1, &val);
3046 btusb_mtk_uhw_reg_read(data, MTK_BT_SUBSYS_RST, &val);
3049 err = readx_poll_timeout(btusb_mtk_reset_done, hdev, val,
3050 val & MTK_BT_RST_DONE, 20000, 1000000);
3054 btusb_mtk_id_get(data, 0x70010200, &val);
3055 if (!val)