Lines Matching refs:map
24 static int regcache_hw_init(struct regmap *map)
32 if (!map->num_reg_defaults_raw)
36 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
37 if (regmap_readable(map, i * map->reg_stride) &&
38 !regmap_volatile(map, i * map->reg_stride))
43 map->cache_bypass = true;
47 map->num_reg_defaults = count;
48 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
50 if (!map->reg_defaults)
53 if (!map->reg_defaults_raw) {
54 bool cache_bypass = map->cache_bypass;
55 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
58 map->cache_bypass = true;
59 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
64 ret = regmap_raw_read(map, 0, tmp_buf,
65 map->cache_size_raw);
66 map->cache_bypass = cache_bypass;
68 map->reg_defaults_raw = tmp_buf;
69 map->cache_free = true;
76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
77 reg = i * map->reg_stride;
79 if (!regmap_readable(map, reg))
82 if (regmap_volatile(map, reg))
85 if (map->reg_defaults_raw) {
86 val = regcache_get_val(map, map->reg_defaults_raw, i);
88 bool cache_bypass = map->cache_bypass;
90 map->cache_bypass = true;
91 ret = regmap_read(map, reg, &val);
92 map->cache_bypass = cache_bypass;
94 dev_err(map->dev, "Failed to read %d: %d\n",
100 map->reg_defaults[j].reg = reg;
101 map->reg_defaults[j].def = val;
108 kfree(map->reg_defaults);
113 int regcache_init(struct regmap *map, const struct regmap_config *config)
119 if (map->cache_type == REGCACHE_NONE) {
121 dev_warn(map->dev,
124 map->cache_bypass = true;
129 dev_err(map->dev,
135 dev_err(map->dev,
141 if (config->reg_defaults[i].reg % map->reg_stride)
145 if (cache_types[i]->type == map->cache_type)
149 dev_err(map->dev, "Could not match cache type: %d\n",
150 map->cache_type);
154 map->num_reg_defaults = config->num_reg_defaults;
155 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
156 map->reg_defaults_raw = config->reg_defaults_raw;
157 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
158 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
160 map->cache = NULL;
161 map->cache_ops = cache_types[i];
163 if (!map->cache_ops->read ||
164 !map->cache_ops->write ||
165 !map->cache_ops->name)
173 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
177 map->reg_defaults = tmp_buf;
178 } else if (map->num_reg_defaults_raw) {
183 ret = regcache_hw_init(map);
186 if (map->cache_bypass)
190 if (!map->max_register && map->num_reg_defaults_raw)
191 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
193 if (map->cache_ops->init) {
194 dev_dbg(map->dev, "Initializing %s cache\n",
195 map->cache_ops->name);
196 ret = map->cache_ops->init(map);
203 kfree(map->reg_defaults);
204 if (map->cache_free)
205 kfree(map->reg_defaults_raw);
210 void regcache_exit(struct regmap *map)
212 if (map->cache_type == REGCACHE_NONE)
215 BUG_ON(!map->cache_ops);
217 kfree(map->reg_defaults);
218 if (map->cache_free)
219 kfree(map->reg_defaults_raw);
221 if (map->cache_ops->exit) {
222 dev_dbg(map->dev, "Destroying %s cache\n",
223 map->cache_ops->name);
224 map->cache_ops->exit(map);
231 * @map: map to configure.
237 int regcache_read(struct regmap *map,
242 if (map->cache_type == REGCACHE_NONE)
245 BUG_ON(!map->cache_ops);
247 if (!regmap_volatile(map, reg)) {
248 ret = map->cache_ops->read(map, reg, value);
251 trace_regmap_reg_read_cache(map, reg, *value);
262 * @map: map to configure.
268 int regcache_write(struct regmap *map,
271 if (map->cache_type == REGCACHE_NONE)
274 BUG_ON(!map->cache_ops);
276 if (!regmap_volatile(map, reg))
277 return map->cache_ops->write(map, reg, value);
282 bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
287 if (!regmap_writeable(map, reg))
291 if (!map->no_sync_defaults)
295 ret = regcache_lookup_reg(map, reg);
296 if (ret >= 0 && val == map->reg_defaults[ret].def)
301 static int regcache_default_sync(struct regmap *map, unsigned int min,
306 for (reg = min; reg <= max; reg += map->reg_stride) {
310 if (regmap_volatile(map, reg) ||
311 !regmap_writeable(map, reg))
314 ret = regcache_read(map, reg, &val);
320 if (!regcache_reg_needs_sync(map, reg, val))
323 map->cache_bypass = true;
324 ret = _regmap_write(map, reg, val);
325 map->cache_bypass = false;
327 dev_err(map->dev, "Unable to sync register %#x. %d\n",
331 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
345 * @map: map to configure.
353 int regcache_sync(struct regmap *map)
361 if (WARN_ON(map->cache_type == REGCACHE_NONE))
364 BUG_ON(!map->cache_ops);
366 map->lock(map->lock_arg);
368 bypass = map->cache_bypass;
369 dev_dbg(map->dev, "Syncing %s cache\n",
370 map->cache_ops->name);
371 name = map->cache_ops->name;
372 trace_regcache_sync(map, name, "start");
374 if (!map->cache_dirty)
378 map->cache_bypass = true;
379 for (i = 0; i < map->patch_regs; i++) {
380 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
382 dev_err(map->dev, "Failed to write %x = %x: %d\n",
383 map->patch[i].reg, map->patch[i].def, ret);
387 map->cache_bypass = false;
389 if (map->cache_ops->sync)
390 ret = map->cache_ops->sync(map, 0, map->max_register);
392 ret = regcache_default_sync(map, 0, map->max_register);
395 map->cache_dirty = false;
399 map->cache_bypass = bypass;
400 map->no_sync_defaults = false;
408 rb_for_each(node, 0, &map->range_tree, rbtree_all) {
413 if (regcache_read(map, this->selector_reg, &i) != 0)
416 ret = _regmap_write(map, this->selector_reg, i);
418 dev_err(map->dev, "Failed to write %x = %x: %d\n",
424 map->unlock(map->lock_arg);
426 regmap_async_complete(map);
428 trace_regcache_sync(map, name, "stop");
437 * @map: map to sync.
446 int regcache_sync_region(struct regmap *map, unsigned int min,
453 if (WARN_ON(map->cache_type == REGCACHE_NONE))
456 BUG_ON(!map->cache_ops);
458 map->lock(map->lock_arg);
461 bypass = map->cache_bypass;
463 name = map->cache_ops->name;
464 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
466 trace_regcache_sync(map, name, "start region");
468 if (!map->cache_dirty)
471 map->async = true;
473 if (map->cache_ops->sync)
474 ret = map->cache_ops->sync(map, min, max);
476 ret = regcache_default_sync(map, min, max);
480 map->cache_bypass = bypass;
481 map->async = false;
482 map->no_sync_defaults = false;
483 map->unlock(map->lock_arg);
485 regmap_async_complete(map);
487 trace_regcache_sync(map, name, "stop region");
496 * @map: map to operate on
504 int regcache_drop_region(struct regmap *map, unsigned int min,
509 if (!map->cache_ops || !map->cache_ops->drop)
512 map->lock(map->lock_arg);
514 trace_regcache_drop_region(map, min, max);
516 ret = map->cache_ops->drop(map, min, max);
518 map->unlock(map->lock_arg);
525 * regcache_cache_only - Put a register map into cache only mode
527 * @map: map to configure
530 * When a register map is marked as cache only writes to the register
531 * map API will only update the register cache, they will not cause
536 void regcache_cache_only(struct regmap *map, bool enable)
538 map->lock(map->lock_arg);
539 WARN_ON(map->cache_type != REGCACHE_NONE &&
540 map->cache_bypass && enable);
541 map->cache_only = enable;
542 trace_regmap_cache_only(map, enable);
543 map->unlock(map->lock_arg);
550 * @map: map to mark
560 void regcache_mark_dirty(struct regmap *map)
562 map->lock(map->lock_arg);
563 map->cache_dirty = true;
564 map->no_sync_defaults = true;
565 map->unlock(map->lock_arg);
570 * regcache_cache_bypass - Put a register map into cache bypass mode
572 * @map: map to configure
575 * When a register map is marked with the cache bypass option, writes
576 * to the register map API will only update the hardware and not
580 void regcache_cache_bypass(struct regmap *map, bool enable)
582 map->lock(map->lock_arg);
583 WARN_ON(map->cache_only && enable);
584 map->cache_bypass = enable;
585 trace_regmap_cache_bypass(map, enable);
586 map->unlock(map->lock_arg);
593 * @map: map to check
598 bool regcache_reg_cached(struct regmap *map, unsigned int reg)
603 map->lock(map->lock_arg);
605 ret = regcache_read(map, reg, &val);
607 map->unlock(map->lock_arg);
613 void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
617 if (map->format.format_val) {
618 map->format.format_val(base + (map->cache_word_size * idx),
623 switch (map->cache_word_size) {
647 unsigned int regcache_get_val(struct regmap *map, const void *base,
654 if (map->format.parse_val)
655 return map->format.parse_val(regcache_get_val_addr(map, base,
658 switch (map->cache_word_size) {
689 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
697 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
701 return r - map->reg_defaults;
714 int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
718 if (!regcache_reg_needs_sync(map, reg, val))
721 map->cache_bypass = true;
723 ret = _regmap_write(map, reg, val);
725 map->cache_bypass = false;
728 dev_err(map->dev, "Unable to sync register %#x. %d\n",
732 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
738 static int regcache_sync_block_single(struct regmap *map, void *block,
747 regtmp = block_base + (i * map->reg_stride);
750 !regmap_writeable(map, regtmp))
753 val = regcache_get_val(map, block, i);
754 ret = regcache_sync_val(map, regtmp, val);
762 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
765 size_t val_bytes = map->format.val_bytes;
771 count = (cur - base) / map->reg_stride;
773 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
774 count * val_bytes, count, base, cur - map->reg_stride);
776 map->cache_bypass = true;
778 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
780 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
781 base, cur - map->reg_stride, ret);
783 map->cache_bypass = false;
790 static int regcache_sync_block_raw(struct regmap *map, void *block,
802 regtmp = block_base + (i * map->reg_stride);
805 !regmap_writeable(map, regtmp)) {
806 ret = regcache_sync_block_raw_flush(map, &data,
813 val = regcache_get_val(map, block, i);
814 if (!regcache_reg_needs_sync(map, regtmp, val)) {
815 ret = regcache_sync_block_raw_flush(map, &data,
823 data = regcache_get_val_addr(map, block, i);
828 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
829 map->reg_stride);
832 int regcache_sync_block(struct regmap *map, void *block,
837 if (regmap_can_raw_write(map) && !map->use_single_write)
838 return regcache_sync_block_raw(map, block, cache_present,
841 return regcache_sync_block_single(map, block, cache_present,