Lines Matching refs:card
26 * 1 - Per card interrupt spinlock (to protect structures and such)
28 * 3 - Per card resource spinlock (to access registers, etc.)
105 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
120 static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
124 static void ns_init_card_error(ns_dev * card, int error);
125 static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126 static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
131 static void fill_tst(ns_dev * card, int n, vc_map * vc);
134 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
136 static void process_tsq(ns_dev * card);
137 static void drain_scq(ns_dev * card, scq_info * scq, int pos);
138 static void process_rsq(ns_dev * card);
139 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
140 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
141 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
142 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
143 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
144 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
148 static void which_list(ns_dev * card, struct sk_buff *skb);
201 ns_dev *card = pci_get_drvdata(pcidev);
207 i = card->index;
212 if (card->atmdev->phy && card->atmdev->phy->stop)
213 card->atmdev->phy->stop(card->atmdev);
216 writel(0x00000000, card->membase + CFG);
219 atm_dev_deregister(card->atmdev);
226 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
227 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
234 card->iovpool.count);
235 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
240 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
242 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
244 free_scq(card, card->scq0, NULL);
246 if (card->scd2vc[j] != NULL)
247 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
249 idr_destroy(&card->idr);
250 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
251 card->rsq.org, card->rsq.dma);
252 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
253 card->tsq.org, card->tsq.dma);
254 free_irq(card->pcidev->irq, card);
255 iounmap(card->membase);
256 kfree(card);
309 static u32 ns_read_sram(ns_dev * card, u32 sram_address)
316 spin_lock_irqsave(&card->res_lock, flags);
317 while (CMD_BUSY(card)) ;
318 writel(sram_address, card->membase + CMD);
319 while (CMD_BUSY(card)) ;
320 data = readl(card->membase + DR0);
321 spin_unlock_irqrestore(&card->res_lock, flags);
325 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
333 spin_lock_irqsave(&card->res_lock, flags);
334 while (CMD_BUSY(card)) ;
336 writel(*(value++), card->membase + i);
338 so card->membase + DR0 == card->membase */
342 writel(sram_address, card->membase + CMD);
343 spin_unlock_irqrestore(&card->res_lock, flags);
349 struct ns_dev *card = NULL;
363 ns_init_card_error(card, error);
370 ns_init_card_error(card, error);
374 card = kmalloc(sizeof(*card), GFP_KERNEL);
375 if (!card) {
380 ns_init_card_error(card, error);
383 cards[i] = card;
384 spin_lock_init(&card->int_lock);
385 spin_lock_init(&card->res_lock);
387 pci_set_drvdata(pcidev, card);
389 card->index = i;
390 card->atmdev = NULL;
391 card->pcidev = pcidev;
393 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
394 if (!card->membase) {
397 ns_init_card_error(card, error);
400 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
407 ns_init_card_error(card, error);
424 ns_init_card_error(card, error);
431 data = readl(card->membase + STAT);
433 writel(NS_STAT_TMROF, card->membase + STAT);
436 writel(NS_CFG_SWRST, card->membase + CFG);
438 writel(0x00000000, card->membase + CFG);
441 writel(0x00000008, card->membase + GP);
443 writel(0x00000001, card->membase + GP);
445 while (CMD_BUSY(card)) ;
446 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
450 while (CMD_BUSY(card)) ;
451 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
452 while (CMD_BUSY(card)) ;
453 data = readl(card->membase + DR0);
457 card->max_pcr = ATM_25_PCR;
458 while (CMD_BUSY(card)) ;
459 writel(0x00000008, card->membase + DR0);
460 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
462 writel(NS_STAT_SFBQF, card->membase + STAT);
464 while (CMD_BUSY(card)) ;
465 writel(0x00000022, card->membase + DR0);
466 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
472 card->max_pcr = ATM_OC3_PCR;
474 while (CMD_BUSY(card)) ;
475 writel(0x00000002, card->membase + DR0);
476 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
482 ns_init_card_error(card, error);
485 writel(0x00000000, card->membase + GP);
489 ns_write_sram(card, 0x1C003, &data, 1);
491 ns_write_sram(card, 0x14003, &data, 1);
492 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
493 ns_read_sram(card, 0x1C003) == 0x76543210)
494 card->sram_size = 128;
496 card->sram_size = 32;
497 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
499 card->rct_size = NS_MAX_RCTSIZE;
502 if (card->sram_size == 128)
507 if (card->sram_size == 32) {
511 card->rct_size = 4096;
517 card->vpibits = NS_VPIBITS;
518 if (card->rct_size == 4096)
519 card->vcibits = 12 - NS_VPIBITS;
520 else /* card->rct_size == 16384 */
521 card->vcibits = 14 - NS_VPIBITS;
525 nicstar_init_eprom(card->membase);
528 writel(0x00000000, card->membase + VPM);
530 card->intcnt = 0;
532 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
535 ns_init_card_error(card, error);
540 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
542 &card->tsq.dma, GFP_KERNEL);
543 if (card->tsq.org == NULL) {
546 ns_init_card_error(card, error);
549 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
550 card->tsq.next = card->tsq.base;
551 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
553 ns_tsi_init(card->tsq.base + j);
554 writel(0x00000000, card->membase + TSQH);
555 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
556 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
559 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
561 &card->rsq.dma, GFP_KERNEL);
562 if (card->rsq.org == NULL) {
565 ns_init_card_error(card, error);
568 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
569 card->rsq.next = card->rsq.base;
570 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
572 ns_rsqe_init(card->rsq.base + j);
573 writel(0x00000000, card->membase + RSQH);
574 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
575 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
578 card->scq1 = NULL;
579 card->scq2 = NULL;
580 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
581 if (card->scq0 == NULL) {
584 ns_init_card_error(card, error);
587 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
591 ns_write_sram(card, NS_VRSCD0, u32d, 4);
592 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
593 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
594 card->scq0->scd = NS_VRSCD0;
595 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
598 card->tst_addr = NS_TST0;
599 card->tst_free_entries = NS_TST_NUM_ENTRIES;
602 ns_write_sram(card, NS_TST0 + j, &data, 1);
604 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
606 ns_write_sram(card, NS_TST1 + j, &data, 1);
608 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
610 card->tste2vc[j] = NULL;
611 writel(NS_TST0 << 2, card->membase + TSTB);
622 for (j = 0; j < card->rct_size; j++)
623 ns_write_sram(card, j * 4, u32d, 4);
625 memset(card->vcmap, 0, sizeof(card->vcmap));
628 card->scd2vc[j] = NULL;
631 card->sbnr.min = MIN_SB;
632 card->sbnr.init = NUM_SB;
633 card->sbnr.max = MAX_SB;
634 card->lbnr.min = MIN_LB;
635 card->lbnr.init = NUM_LB;
636 card->lbnr.max = MAX_LB;
637 card->iovnr.min = MIN_IOVB;
638 card->iovnr.init = NUM_IOVB;
639 card->iovnr.max = MAX_IOVB;
640 card->hbnr.min = MIN_HB;
641 card->hbnr.init = NUM_HB;
642 card->hbnr.max = MAX_HB;
644 card->sm_handle = NULL;
645 card->sm_addr = 0x00000000;
646 card->lg_handle = NULL;
647 card->lg_addr = 0x00000000;
649 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
651 idr_init(&card->idr);
654 skb_queue_head_init(&card->hbpool.queue);
655 card->hbpool.count = 0;
664 ns_init_card_error(card, error);
668 skb_queue_tail(&card->hbpool.queue, hb);
669 card->hbpool.count++;
673 skb_queue_head_init(&card->lbpool.queue);
674 card->lbpool.count = 0; /* Not used */
683 ns_init_card_error(card, error);
687 skb_queue_tail(&card->lbpool.queue, lb);
689 push_rxbufs(card, lb);
692 card->rcbuf = lb;
693 card->rawcell = (struct ns_rcqe *) lb->data;
694 card->rawch = NS_PRV_DMA(lb);
699 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
704 ns_init_card_error(card, error);
709 skb_queue_head_init(&card->sbpool.queue);
710 card->sbpool.count = 0; /* Not used */
719 ns_init_card_error(card, error);
723 skb_queue_tail(&card->sbpool.queue, sb);
725 push_rxbufs(card, sb);
729 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
734 ns_init_card_error(card, error);
739 skb_queue_head_init(&card->iovpool.queue);
740 card->iovpool.count = 0;
749 ns_init_card_error(card, error);
753 skb_queue_tail(&card->iovpool.queue, iovb);
754 card->iovpool.count++;
758 if (card->rct_size == 4096)
760 else /* (card->rct_size == 16384) */
763 card->efbie = 1;
766 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
768 if (card->atmdev == NULL) {
771 ns_init_card_error(card, error);
775 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
776 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
777 card->atmdev->esi, 6);
778 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
779 nicstar_read_eprom(card->membase,
781 card->atmdev->esi, 6);
785 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
787 card->atmdev->dev_data = card;
788 card->atmdev->ci_range.vpi_bits = card->vpibits;
789 card->atmdev->ci_range.vci_bits = card->vcibits;
790 card->atmdev->link_rate = card->max_pcr;
791 card->atmdev->phy = NULL;
794 if (card->max_pcr == ATM_OC3_PCR)
795 suni_init(card->atmdev);
799 if (card->max_pcr == ATM_25_PCR)
800 idt77105_init(card->atmdev);
803 if (card->atmdev->phy && card->atmdev->phy->start)
804 card->atmdev->phy->start(card->atmdev);
808 NS_CFG_PHYIE, card->membase + CFG);
815 static void ns_init_card_error(ns_dev *card, int error)
818 writel(0x00000000, card->membase + CFG);
822 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
827 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
829 free_scq(card, card->scq0, NULL);
833 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
838 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
842 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
843 card->rsq.org, card->rsq.dma);
846 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
847 card->tsq.org, card->tsq.dma);
850 free_irq(card->pcidev->irq, card);
853 iounmap(card->membase);
856 pci_disable_device(card->pcidev);
857 kfree(card);
861 static scq_info *get_scq(ns_dev *card, int size, u32 scd)
871 scq->org = dma_alloc_coherent(&card->pcidev->dev,
880 dma_free_coherent(&card->pcidev->dev,
900 static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
931 dma_free_coherent(&card->pcidev->dev,
940 static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
952 addr1 = dma_map_single(&card->pcidev->dev,
962 card->index);
965 stat = readl(card->membase + STAT);
966 card->sbfqc = ns_stat_sfbqc_get(stat);
967 card->lbfqc = ns_stat_lfbqc_get(stat);
970 if (card->sm_addr) {
971 addr2 = card->sm_addr;
972 handle2 = card->sm_handle;
973 card->sm_addr = 0x00000000;
974 card->sm_handle = NULL;
977 card->sm_addr = addr1;
978 card->sm_handle = handle1;
984 if (card->lg_addr) {
985 addr2 = card->lg_addr;
986 handle2 = card->lg_handle;
987 card->lg_addr = 0x00000000;
988 card->lg_handle = NULL;
991 card->lg_addr = addr1;
992 card->lg_handle = handle1;
999 if (card->sbfqc >= card->sbnr.max) {
1000 skb_unlink(handle1, &card->sbpool.queue);
1002 skb_unlink(handle2, &card->sbpool.queue);
1006 card->sbfqc += 2;
1009 if (card->lbfqc >= card->lbnr.max) {
1010 skb_unlink(handle1, &card->lbpool.queue);
1012 skb_unlink(handle2, &card->lbpool.queue);
1016 card->lbfqc += 2;
1019 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1023 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1027 spin_lock_irqsave(&card->res_lock, flags);
1028 while (CMD_BUSY(card)) ;
1029 writel(addr2, card->membase + DR3);
1030 writel(id2, card->membase + DR2);
1031 writel(addr1, card->membase + DR1);
1032 writel(id1, card->membase + DR0);
1034 card->membase + CMD);
1035 spin_unlock_irqrestore(&card->res_lock, flags);
1038 card->index,
1043 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1044 card->lbfqc >= card->lbnr.min) {
1045 card->efbie = 1;
1046 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1047 card->membase + CFG);
1057 ns_dev *card;
1061 card = (ns_dev *) dev_id;
1062 dev = card->atmdev;
1063 card->intcnt++;
1065 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1067 spin_lock_irqsave(&card->int_lock, flags);
1069 stat_r = readl(card->membase + STAT);
1073 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1074 process_tsq(card);
1075 writel(NS_STAT_TSIF, card->membase + STAT);
1080 writel(NS_STAT_TXICP, card->membase + STAT);
1082 card->index);
1087 writel(NS_STAT_TSQF, card->membase + STAT);
1088 PRINTK("nicstar%d: TSQ full.\n", card->index);
1089 process_tsq(card);
1094 writel(NS_STAT_TMROF, card->membase + STAT);
1095 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1100 writel(NS_STAT_PHYI, card->membase + STAT);
1101 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1109 writel(NS_STAT_SFBQF, card->membase + STAT);
1111 card->index);
1116 writel(NS_STAT_LFBQF, card->membase + STAT);
1118 card->index);
1123 writel(NS_STAT_RSQF, card->membase + STAT);
1124 printk("nicstar%d: RSQ full.\n", card->index);
1125 process_rsq(card);
1130 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1131 process_rsq(card);
1132 writel(NS_STAT_EOPDU, card->membase + STAT);
1137 writel(NS_STAT_RAWCF, card->membase + STAT);
1140 card->index);
1145 while (readl(card->membase + RAWCT) != card->rawch) {
1147 if (ns_rcqe_islast(card->rawcell)) {
1150 oldbuf = card->rcbuf;
1151 card->rcbuf = idr_find(&card->idr,
1152 ns_rcqe_nextbufhandle(card->rawcell));
1153 card->rawch = NS_PRV_DMA(card->rcbuf);
1154 card->rawcell = (struct ns_rcqe *)
1155 card->rcbuf->data;
1156 recycle_rx_buf(card, oldbuf);
1158 card->rawch += NS_RCQE_SIZE;
1159 card->rawcell++;
1169 writel(NS_STAT_SFBQE, card->membase + STAT);
1171 card->index);
1172 for (i = 0; i < card->sbnr.min; i++) {
1175 writel(readl(card->membase + CFG) &
1176 ~NS_CFG_EFBIE, card->membase + CFG);
1177 card->efbie = 0;
1181 skb_queue_tail(&card->sbpool.queue, sb);
1183 push_rxbufs(card, sb);
1185 card->sbfqc = i;
1186 process_rsq(card);
1194 writel(NS_STAT_LFBQE, card->membase + STAT);
1196 card->index);
1197 for (i = 0; i < card->lbnr.min; i++) {
1200 writel(readl(card->membase + CFG) &
1201 ~NS_CFG_EFBIE, card->membase + CFG);
1202 card->efbie = 0;
1206 skb_queue_tail(&card->lbpool.queue, lb);
1208 push_rxbufs(card, lb);
1210 card->lbfqc = i;
1211 process_rsq(card);
1216 writel(NS_STAT_RSQAF, card->membase + STAT);
1217 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1218 process_rsq(card);
1221 spin_unlock_irqrestore(&card->int_lock, flags);
1222 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1228 ns_dev *card;
1243 card = (ns_dev *) vcc->dev->dev_data;
1244 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1247 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1251 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1260 printk("nicstar%d: %s vci already in use.\n", card->index,
1280 card->index);
1290 card->index, vcc->qos.txtp.max_pcr);
1295 modl = tmpl % card->max_pcr;
1297 n = (int)(tmpl / card->max_pcr);
1303 (card->tst_free_entries -
1307 card->index);
1317 card->index);
1323 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1326 card->index);
1331 card->tst_free_entries -= n;
1334 card->index, n);
1336 if (card->scd2vc[frscdi] == NULL) {
1337 card->scd2vc[frscdi] = vc;
1344 card->index);
1345 card->tst_free_entries += n;
1353 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1356 card->index);
1357 card->scd2vc[frscdi] = NULL;
1358 card->tst_free_entries += n;
1368 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1370 fill_tst(card, n, vc);
1373 vc->scq = card->scq0;
1396 ns_write_sram(card,
1398 (vpi << card->vcibits | vci) *
1411 ns_dev *card;
1416 card = vcc->dev->dev_data;
1417 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1428 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1429 spin_lock_irqsave(&card->res_lock, flags);
1430 while (CMD_BUSY(card)) ;
1432 card->membase + CMD);
1433 spin_unlock_irqrestore(&card->res_lock, flags);
1440 stat = readl(card->membase + STAT);
1441 card->sbfqc = ns_stat_sfbqc_get(stat);
1442 card->lbfqc = ns_stat_lfbqc_get(stat);
1446 card->index);
1448 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1451 spin_lock_irqsave(&card->int_lock, flags);
1452 recycle_iov_buf(card, iovb);
1453 spin_unlock_irqrestore(&card->int_lock, flags);
1502 ns_write_sram(card, scq->scd, &data, 1);
1511 if (card->tste2vc[i] == vc) {
1512 ns_write_sram(card, card->tst_addr + i, &data,
1514 card->tste2vc[i] = NULL;
1515 card->tst_free_entries++;
1519 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1520 free_scq(card, vc->scq, vcc);
1526 scq_info *scq = card->scq0;
1549 stat = readl(card->membase + STAT);
1550 cfg = readl(card->membase + CFG);
1554 card->tsq.base, card->tsq.next,
1555 card->tsq.last, readl(card->membase + TSQT));
1558 card->rsq.base, card->rsq.next,
1559 card->rsq.last, readl(card->membase + RSQT));
1561 card->efbie ? "enabled" : "disabled");
1563 ns_stat_sfbqc_get(stat), card->sbpool.count,
1564 ns_stat_lfbqc_get(stat), card->lbpool.count);
1566 card->hbpool.count, card->iovpool.count);
1571 static void fill_tst(ns_dev * card, int n, vc_map * vc)
1582 new_tst = card->tst_addr;
1587 if (card->tste2vc[e] == NULL)
1591 printk("nicstar%d: No free TST entries found. \n", card->index);
1600 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1601 card->tste2vc[e] = vc;
1602 ns_write_sram(card, new_tst + e, &data, 1);
1616 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1617 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1618 card->tst_addr = new_tst;
1623 ns_dev *card;
1630 card = vcc->dev->dev_data;
1631 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1634 card->index);
1642 card->index);
1650 card->index);
1657 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1665 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1702 scq = card->scq0;
1705 if (push_scqe(card, vc, scq, &scqe, skb, may_sleep) != 0) {
1707 dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
1727 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1741 printk("nicstar%d: Error pushing TBD.\n", card->index);
1754 card->index);
1762 card->index, skb, index);
1764 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1786 ns_write_sram(card, scq->scd, &data, 1);
1789 card->index);
1818 card->index, le32_to_cpu(tsr.word_1),
1829 card->index);
1832 ns_write_sram(card, scq->scd, &data, 1);
1839 static void process_tsq(ns_dev * card)
1848 if (card->tsq.next == card->tsq.last)
1849 one_ahead = card->tsq.base;
1851 one_ahead = card->tsq.next + 1;
1853 if (one_ahead == card->tsq.last)
1854 two_ahead = card->tsq.base;
1858 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1865 while (ns_tsi_isempty(card->tsq.next)) {
1866 if (card->tsq.next == card->tsq.last)
1867 card->tsq.next = card->tsq.base;
1869 card->tsq.next++;
1872 if (!ns_tsi_tmrof(card->tsq.next)) {
1873 scdi = ns_tsi_getscdindex(card->tsq.next);
1875 scq = card->scq0;
1877 if (card->scd2vc[scdi] == NULL) {
1880 card->index);
1881 ns_tsi_init(card->tsq.next);
1884 scq = card->scd2vc[scdi]->scq;
1886 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1891 ns_tsi_init(card->tsq.next);
1892 previous = card->tsq.next;
1893 if (card->tsq.next == card->tsq.last)
1894 card->tsq.next = card->tsq.base;
1896 card->tsq.next++;
1898 if (card->tsq.next == card->tsq.last)
1899 one_ahead = card->tsq.base;
1901 one_ahead = card->tsq.next + 1;
1903 if (one_ahead == card->tsq.last)
1904 two_ahead = card->tsq.base;
1910 writel(PTR_DIFF(previous, card->tsq.base),
1911 card->membase + TSQH);
1914 static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1922 card->index, scq, pos);
1924 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1935 card->index, skb, i);
1937 dma_unmap_single(&card->pcidev->dev,
1956 static void process_rsq(ns_dev * card)
1960 if (!ns_rsqe_valid(card->rsq.next))
1963 dequeue_rx(card, card->rsq.next);
1964 ns_rsqe_init(card->rsq.next);
1965 previous = card->rsq.next;
1966 if (card->rsq.next == card->rsq.last)
1967 card->rsq.next = card->rsq.base;
1969 card->rsq.next++;
1970 } while (ns_rsqe_valid(card->rsq.next));
1971 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1974 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1987 stat = readl(card->membase + STAT);
1988 card->sbfqc = ns_stat_sfbqc_get(stat);
1989 card->lbfqc = ns_stat_lfbqc_get(stat);
1992 skb = idr_remove(&card->idr, id);
1995 "nicstar%d: skb not found!\n", card->index);
1998 dma_sync_single_for_cpu(&card->pcidev->dev,
2003 dma_unmap_single(&card->pcidev->dev,
2010 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2012 card->index, vpi, vci);
2013 recycle_rx_buf(card, skb);
2017 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2020 card->index, vpi, vci);
2021 recycle_rx_buf(card, skb);
2038 card->index);
2045 card->index);
2065 recycle_rx_buf(card, skb);
2072 iovb = skb_dequeue(&(card->iovpool.queue));
2077 card->index);
2079 recycle_rx_buf(card, skb);
2083 } else if (--card->iovpool.count < card->iovnr.min) {
2088 skb_queue_tail(&card->iovpool.queue, new_iovb);
2089 card->iovpool.count++;
2101 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2103 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2120 card->index);
2121 which_list(card, skb);
2123 recycle_rx_buf(card, skb);
2125 recycle_iov_buf(card, iovb);
2133 card->index);
2134 which_list(card, skb);
2136 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2139 recycle_iov_buf(card, iovb);
2153 printk("nicstar%d: AAL5 CRC error", card->index);
2159 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2162 recycle_iov_buf(card, iovb);
2171 push_rxbufs(card, skb);
2175 dequeue_sm_buf(card, skb);
2189 push_rxbufs(card, sb);
2193 dequeue_sm_buf(card, sb);
2200 push_rxbufs(card, skb);
2205 push_rxbufs(card, skb);
2208 dequeue_lg_buf(card, skb);
2219 push_rxbufs(card, sb);
2229 hb = skb_dequeue(&(card->hbpool.queue));
2236 card->index);
2238 recycle_iovec_rx_bufs(card,
2243 recycle_iov_buf(card, iovb);
2245 } else if (card->hbpool.count < card->hbnr.min) {
2250 skb_queue_tail(&card->hbpool.
2252 card->hbpool.count++;
2256 } else if (--card->hbpool.count < card->hbnr.min) {
2261 skb_queue_tail(&card->hbpool.queue,
2263 card->hbpool.count++;
2265 if (card->hbpool.count < card->hbnr.min) {
2271 skb_queue_tail(&card->hbpool.
2273 card->hbpool.count++;
2281 recycle_iovec_rx_bufs(card, iov,
2283 if (card->hbpool.count < card->hbnr.max) {
2284 skb_queue_tail(&card->hbpool.queue, hb);
2285 card->hbpool.count++;
2298 push_rxbufs(card, sb);
2311 push_rxbufs(card, lb);
2317 card->index);
2327 recycle_iov_buf(card, iovb);
2332 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2336 card->index);
2339 push_rxbufs(card, skb);
2342 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2345 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2348 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2350 if (card->iovpool.count < card->iovnr.max) {
2351 skb_queue_tail(&card->iovpool.queue, iovb);
2352 card->iovpool.count++;
2357 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2359 skb_unlink(sb, &card->sbpool.queue);
2360 if (card->sbfqc < card->sbnr.init) {
2364 skb_queue_tail(&card->sbpool.queue, new_sb);
2366 push_rxbufs(card, new_sb);
2369 if (card->sbfqc < card->sbnr.init)
2374 skb_queue_tail(&card->sbpool.queue, new_sb);
2376 push_rxbufs(card, new_sb);
2381 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2383 skb_unlink(lb, &card->lbpool.queue);
2384 if (card->lbfqc < card->lbnr.init) {
2388 skb_queue_tail(&card->lbpool.queue, new_lb);
2390 push_rxbufs(card, new_lb);
2393 if (card->lbfqc < card->lbnr.init)
2398 skb_queue_tail(&card->lbpool.queue, new_lb);
2400 push_rxbufs(card, new_lb);
2408 ns_dev *card;
2412 card = (ns_dev *) dev->dev_data;
2413 stat = readl(card->membase + STAT);
2418 ns_stat_sfbqc_get(stat), card->sbnr.min,
2419 card->sbnr.init, card->sbnr.max);
2422 ns_stat_lfbqc_get(stat), card->lbnr.min,
2423 card->lbnr.init, card->lbnr.max);
2426 card->hbpool.count, card->hbnr.min,
2427 card->hbnr.init, card->hbnr.max);
2430 card->iovpool.count, card->iovnr.min,
2431 card->iovnr.init, card->iovnr.max);
2435 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2436 card->intcnt = 0;
2443 if (card->max_pcr == ATM_25_PCR && !left--) {
2448 while (CMD_BUSY(card)) ;
2450 card->membase + CMD);
2451 while (CMD_BUSY(card)) ;
2452 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2463 if (card->tste2vc[left + 1] == NULL)
2467 card->tste2vc[left + 1]->tx_vcc->vpi,
2468 card->tste2vc[left + 1]->tx_vcc->vci);
2476 ns_dev *card;
2481 card = dev->dev_data;
2490 ns_stat_sfbqc_get(readl(card->membase + STAT));
2491 pl.level.min = card->sbnr.min;
2492 pl.level.init = card->sbnr.init;
2493 pl.level.max = card->sbnr.max;
2498 ns_stat_lfbqc_get(readl(card->membase + STAT));
2499 pl.level.min = card->lbnr.min;
2500 pl.level.init = card->lbnr.init;
2501 pl.level.max = card->lbnr.max;
2505 pl.count = card->hbpool.count;
2506 pl.level.min = card->hbnr.min;
2507 pl.level.init = card->hbnr.init;
2508 pl.level.max = card->hbnr.max;
2512 pl.count = card->iovpool.count;
2513 pl.level.min = card->iovnr.min;
2514 pl.level.init = card->iovnr.init;
2515 pl.level.max = card->iovnr.max;
2541 card->sbnr.min = pl.level.min;
2542 card->sbnr.init = pl.level.init;
2543 card->sbnr.max = pl.level.max;
2549 card->lbnr.min = pl.level.min;
2550 card->lbnr.init = pl.level.init;
2551 card->lbnr.max = pl.level.max;
2557 card->hbnr.min = pl.level.min;
2558 card->hbnr.init = pl.level.init;
2559 card->hbnr.max = pl.level.max;
2565 card->iovnr.min = pl.level.min;
2566 card->iovnr.init = pl.level.init;
2567 card->iovnr.max = pl.level.max;
2582 while (card->sbfqc < card->sbnr.init) {
2589 skb_queue_tail(&card->sbpool.queue, sb);
2591 push_rxbufs(card, sb);
2596 while (card->lbfqc < card->lbnr.init) {
2603 skb_queue_tail(&card->lbpool.queue, lb);
2605 push_rxbufs(card, lb);
2610 while (card->hbpool.count > card->hbnr.init) {
2613 spin_lock_irqsave(&card->int_lock, flags);
2614 hb = skb_dequeue(&card->hbpool.queue);
2615 card->hbpool.count--;
2616 spin_unlock_irqrestore(&card->int_lock, flags);
2620 card->index);
2625 while (card->hbpool.count < card->hbnr.init) {
2632 spin_lock_irqsave(&card->int_lock, flags);
2633 skb_queue_tail(&card->hbpool.queue, hb);
2634 card->hbpool.count++;
2635 spin_unlock_irqrestore(&card->int_lock, flags);
2640 while (card->iovpool.count > card->iovnr.init) {
2643 spin_lock_irqsave(&card->int_lock, flags);
2644 iovb = skb_dequeue(&card->iovpool.queue);
2645 card->iovpool.count--;
2646 spin_unlock_irqrestore(&card->int_lock, flags);
2650 card->index);
2655 while (card->iovpool.count < card->iovnr.init) {
2662 spin_lock_irqsave(&card->int_lock, flags);
2663 skb_queue_tail(&card->iovpool.queue, iovb);
2664 card->iovpool.count++;
2665 spin_unlock_irqrestore(&card->int_lock, flags);
2679 printk("nicstar%d: %s == NULL \n", card->index,
2687 static void which_list(ns_dev * card, struct sk_buff *skb)
2696 ns_dev *card;
2702 card = cards[i];
2703 if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2709 stat_r = readl(card->membase + STAT);
2715 process_tsq(card);
2716 process_rsq(card);
2718 writel(stat_w, card->membase + STAT);
2719 spin_unlock_irqrestore(&card->int_lock, flags);
2728 ns_dev *card;
2731 card = dev->dev_data;
2732 spin_lock_irqsave(&card->res_lock, flags);
2733 while (CMD_BUSY(card)) ;
2734 writel((u32) value, card->membase + DR0);
2736 card->membase + CMD);
2737 spin_unlock_irqrestore(&card->res_lock, flags);
2742 ns_dev *card;
2746 card = dev->dev_data;
2747 spin_lock_irqsave(&card->res_lock, flags);
2748 while (CMD_BUSY(card)) ;
2750 card->membase + CMD);
2751 while (CMD_BUSY(card)) ;
2752 data = readl(card->membase + DR0) & 0x000000FF;
2753 spin_unlock_irqrestore(&card->res_lock, flags);