Lines Matching defs:lanai
2 /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com>
160 #define DEV_LABEL "lanai"
302 static void vci_bitfield_iterate(struct lanai_dev *lanai,
309 func(lanai, vci);
333 if (bytes > (128 * 1024)) /* max lanai buffer size */
342 * everything, but the way the lanai uses DMA memory would
439 #define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */
468 static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
471 return lanai->base + reg;
474 static inline u32 reg_read(const struct lanai_dev *lanai,
478 t = readl(reg_addr(lanai, reg));
479 RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
484 static inline void reg_write(const struct lanai_dev *lanai, u32 val,
487 RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
489 writel(val, reg_addr(lanai, reg));
492 static inline void conf1_write(const struct lanai_dev *lanai)
494 reg_write(lanai, lanai->conf1, Config1_Reg);
497 static inline void conf2_write(const struct lanai_dev *lanai)
499 reg_write(lanai, lanai->conf2, Config2_Reg);
503 static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)
506 if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))
509 conf2_write(lanai);
512 static inline void reset_board(const struct lanai_dev *lanai)
515 reg_write(lanai, 0, Reset_Reg);
535 static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
537 return lanai->base + SRAM_START + offset;
540 static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
542 return readl(sram_addr(lanai, offset));
545 static inline void sram_write(const struct lanai_dev *lanai,
548 writel(val, sram_addr(lanai, offset));
551 static int sram_test_word(const struct lanai_dev *lanai, int offset,
555 sram_write(lanai, pattern, offset);
556 readback = sram_read(lanai, offset);
561 lanai->number, offset,
566 static int sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
570 result = sram_test_word(lanai, offset, pattern);
574 static int sram_test_and_clear(const struct lanai_dev *lanai)
579 if ((result = sram_test_pass(lanai, 0x5555)) != 0)
581 if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
585 return sram_test_pass(lanai, 0x0000);
640 static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
643 return sram_addr(lanai, vci * CARDVCC_SIZE);
756 * Unfortunately the lanai needs us to wait until all the data
762 static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
775 __clear_bit(lvcc->vci, lanai->backlog_vccs);
817 static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
820 lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,
821 lanai->pci);
822 return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;
825 static inline void aal0_buffer_free(struct lanai_dev *lanai)
828 lanai_buf_deallocate(&lanai->aal0buf, lanai->pci);
850 static int eeprom_read(struct lanai_dev *lanai)
853 lanai->number);
854 memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
858 static int eeprom_validate(struct lanai_dev *lanai)
860 lanai->serialno = 0;
861 lanai->magicno = EEPROM_MAGIC_VALUE;
867 static int eeprom_read(struct lanai_dev *lanai)
872 #define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \
874 #define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK)
875 #define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
876 #define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA)
877 #define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
879 #define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
890 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
892 if (lanai->conf1 != tmp) {
915 lanai->eeprom[address] = data;
924 lanai->number, address);
937 static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
939 return be32_to_cpup((const u32 *) &lanai->eeprom[address]);
943 static int eeprom_validate(struct lanai_dev *lanai)
947 const u8 *e = lanai->eeprom;
967 "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
974 "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
983 "(0x%02X, inverse 0x%02X)\n", lanai->number,
990 lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
991 v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
992 if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
994 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
995 (unsigned int) lanai->serialno, (unsigned int) v);
998 DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno);
1000 lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
1001 v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
1002 if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
1004 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1005 lanai->magicno, v);
1008 DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
1009 if (lanai->magicno != EEPROM_MAGIC_VALUE)
1012 lanai->number, (unsigned int) lanai->magicno,
1019 static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
1021 return &lanai->eeprom[EEPROM_MAC];
1040 #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */
1051 static inline u32 intr_pending(const struct lanai_dev *lanai)
1053 return reg_read(lanai, IntStatusMasked_Reg);
1056 static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
1058 reg_write(lanai, i, IntControlEna_Reg);
1061 static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
1063 reg_write(lanai, i, IntControlDis_Reg);
1075 static void lanai_check_status(struct lanai_dev *lanai)
1077 u32 new = reg_read(lanai, Status_Reg);
1078 u32 changes = new ^ lanai->status;
1079 lanai->status = new;
1082 status_message(lanai->number, name, new & flag)
1095 static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
1099 result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
1102 "%d\n", lanai->number, result);
1110 result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
1113 "%d\n", lanai->number, result);
1118 pcistatus_got(lanai->number, name); \
1119 ++lanai->stats.pcierr_##stat; \
1232 static inline void lanai_endtx(struct lanai_dev *lanai,
1248 spin_lock(&lanai->endtxlock);
1255 for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
1258 "always busy!\n", lanai->number);
1269 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
1270 spin_unlock(&lanai->endtxlock);
1277 static void lanai_send_one_aal5(struct lanai_dev *lanai,
1291 lanai_endtx(lanai, lvcc);
1297 static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
1316 lanai_send_one_aal5(lanai, lvcc, skb, n);
1321 __clear_bit(lvcc->vci, lanai->backlog_vccs);
1326 static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1337 __set_bit(lvcc->vci, lanai->backlog_vccs);
1342 lanai_send_one_aal5(lanai, lvcc, skb, n);
1345 static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
1352 static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1422 static void vcc_rx_aal0(struct lanai_dev *lanai)
1438 static int vcc_table_allocate(struct lanai_dev *lanai)
1441 APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
1443 lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);
1444 return (lanai->vccs == NULL) ? -ENOMEM : 0;
1446 int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
1447 lanai->vccs = vzalloc(bytes);
1448 if (unlikely(lanai->vccs == NULL))
1454 static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
1457 free_page((unsigned long) lanai->vccs);
1459 vfree(lanai->vccs);
1477 static int lanai_get_sized_buffer(struct lanai_dev *lanai,
1486 lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);
1491 "for %s buffer, got only %zu\n", lanai->number, size,
1498 static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,
1501 return lanai_get_sized_buffer(lanai, &lvcc->rx.buf,
1506 static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1519 return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,
1523 static inline void host_vcc_bind(struct lanai_dev *lanai,
1530 if (lanai->nbound++ == 0) {
1532 lanai->conf1 &= ~CONFIG1_POWERDOWN;
1533 conf1_write(lanai);
1534 conf2_write(lanai);
1537 lvcc->vbase = cardvcc_addr(lanai, vci);
1538 lanai->vccs[lvcc->vci = vci] = lvcc;
1541 static inline void host_vcc_unbind(struct lanai_dev *lanai,
1548 lanai->vccs[lvcc->vci] = NULL;
1550 if (--lanai->nbound == 0) {
1552 lanai->conf1 |= CONFIG1_POWERDOWN;
1553 conf1_write(lanai);
1560 static void lanai_reset(struct lanai_dev *lanai)
1563 "implemented\n", lanai->number);
1569 reg_write(lanai, INT_ALL, IntAck_Reg);
1570 lanai->stats.card_reset++;
1578 static int service_buffer_allocate(struct lanai_dev *lanai)
1580 lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,
1581 lanai->pci);
1582 if (unlikely(lanai->service.start == NULL))
1585 lanai->service.start,
1586 lanai_buf_size(&lanai->service),
1587 lanai_buf_size_cardorder(&lanai->service));
1589 reg_write(lanai, 0, ServWrite_Reg);
1591 reg_write(lanai,
1592 SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
1593 SSTUFF_SET_ADDR(lanai->service.dmaaddr),
1598 static inline void service_buffer_deallocate(struct lanai_dev *lanai)
1600 lanai_buf_deallocate(&lanai->service, lanai->pci);
1616 static int handle_service(struct lanai_dev *lanai, u32 s)
1621 lvcc = lanai->vccs[vci];
1625 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1627 lanai->stats.service_notx++;
1629 lanai->stats.service_norx++;
1636 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1637 lanai->stats.service_notx++;
1640 __set_bit(vci, lanai->transmit_ready);
1648 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1649 lanai->stats.service_norx++;
1655 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1656 lanai->stats.service_rxnotaal5++;
1676 lanai->stats.ovfl_trash += (bytes / 48);
1684 "PDU on VCI %d!\n", lanai->number, vci);
1685 lanai_reset(lanai);
1698 static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
1700 struct lanai_vcc *lvcc = lanai->vccs[vci];
1702 lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
1706 * interrupts otherwise disabled and with the lanai->servicelock
1709 static void run_service(struct lanai_dev *lanai)
1712 u32 wreg = reg_read(lanai, ServWrite_Reg);
1713 const u32 *end = lanai->service.start + wreg;
1714 while (lanai->service.ptr != end) {
1715 ntx += handle_service(lanai,
1716 le32_to_cpup(lanai->service.ptr++));
1717 if (lanai->service.ptr >= lanai->service.end)
1718 lanai->service.ptr = lanai->service.start;
1720 reg_write(lanai, wreg, ServRead_Reg);
1723 vci_bitfield_iterate(lanai, lanai->transmit_ready,
1725 bitmap_zero(lanai->transmit_ready, NUM_VCI);
1732 static void get_statistics(struct lanai_dev *lanai)
1734 u32 statreg = reg_read(lanai, Statistics_Reg);
1735 lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
1736 lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
1737 lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
1738 lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
1745 static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
1747 struct lanai_vcc *lvcc = lanai->vccs[vci];
1751 __clear_bit(vci, lanai->backlog_vccs);
1755 lvcc->tx.unqueue(lanai, lvcc, endptr);
1761 struct lanai_dev *lanai = from_timer(lanai, t, timer);
1765 if (lanai->conf1 & CONFIG1_POWERDOWN)
1770 if (spin_trylock(&lanai->servicelock)) {
1771 run_service(lanai);
1772 spin_unlock(&lanai->servicelock);
1777 vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);
1781 get_statistics(lanai);
1783 mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
1786 static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
1788 timer_setup(&lanai->timer, lanai_timed_poll, 0);
1789 lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
1790 add_timer(&lanai->timer);
1793 static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
1795 del_timer_sync(&lanai->timer);
1800 static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
1805 spin_lock(&lanai->servicelock);
1806 run_service(lanai);
1807 spin_unlock(&lanai->servicelock);
1811 vcc_rx_aal0(lanai);
1818 get_statistics(lanai);
1822 lanai_check_status(lanai);
1827 lanai->number, (unsigned int) (reason & INT_DMASHUT),
1828 (unsigned int) reg_read(lanai, DMA_Addr_Reg));
1830 lanai_reset(lanai);
1835 lanai->number);
1836 conf1_write(lanai);
1837 lanai->stats.dma_reenable++;
1838 pcistatus_check(lanai, 0);
1843 lanai->number);
1844 pcistatus_check(lanai, 0);
1848 "segmentation shutdown, reason=0x%08X\n", lanai->number,
1850 lanai_reset(lanai);
1856 lanai->number,
1858 lanai_reset(lanai);
1870 reg_write(lanai, ack, IntAck_Reg);
1875 struct lanai_dev *lanai = devid;
1884 if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))
1888 reason = intr_pending(lanai);
1895 lanai_int_1(lanai, reason);
1896 reason = intr_pending(lanai);
1930 static int lanai_pci_start(struct lanai_dev *lanai)
1932 struct pci_dev *pci = lanai->pci;
1937 "PCI device", lanai->number);
1943 "(itf %d): No suitable DMA available.\n", lanai->number);
1949 /* Set latency timer to zero as per lanai docs */
1953 "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
1956 pcistatus_check(lanai, 1);
1957 pcistatus_check(lanai, 0);
1969 static inline int vci0_is_ok(struct lanai_dev *lanai,
1975 if (lanai->naal0 != 0)
1977 lanai->conf2 |= CONFIG2_VCI0_NORMAL;
1978 conf2_write_if_powerup(lanai);
1986 static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
1990 const struct lanai_vcc *lvcc = lanai->vccs[vci];
1991 if (vci == 0 && !vci0_is_ok(lanai, qos))
2001 lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
2004 if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
2006 const struct lanai_vcc *vci0 = lanai->vccs[0];
2009 lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
2010 conf2_write_if_powerup(lanai);
2015 static int lanai_normalize_ci(struct lanai_dev *lanai,
2029 for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
2031 if (vci_is_ok(lanai, *vcip, atmvcc))
2035 if (*vcip >= lanai->num_vci || *vcip < 0 ||
2036 !vci_is_ok(lanai, *vcip, atmvcc))
2089 static inline void lanai_cbr_setup(struct lanai_dev *lanai)
2091 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
2092 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
2093 lanai->conf2 |= CONFIG2_CBR_ENABLE;
2094 conf2_write(lanai);
2097 static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
2099 lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
2100 conf2_write(lanai);
2108 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2114 lanai->number = atmdev->number;
2115 lanai->num_vci = NUM_VCI;
2116 bitmap_zero(lanai->backlog_vccs, NUM_VCI);
2117 bitmap_zero(lanai->transmit_ready, NUM_VCI);
2118 lanai->naal0 = 0;
2120 lanai->nbound = 0;
2122 lanai->cbrvcc = NULL;
2123 memset(&lanai->stats, 0, sizeof lanai->stats);
2124 spin_lock_init(&lanai->endtxlock);
2125 spin_lock_init(&lanai->servicelock);
2128 while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
2133 if ((result = lanai_pci_start(lanai)) != 0)
2135 raw_base = lanai->pci->resource[0].start;
2136 lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
2137 if (lanai->base == NULL) {
2142 /* 3.3: Reset lanai and PHY */
2143 reset_board(lanai);
2144 lanai->conf1 = reg_read(lanai, Config1_Reg);
2145 lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
2147 lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
2148 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2150 conf1_write(lanai);
2162 reg_read(lanai, Reset_Reg), &lanai->board_rev);
2167 if ((result = eeprom_read(lanai)) != 0)
2169 if ((result = eeprom_validate(lanai)) != 0)
2173 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2175 conf1_write(lanai);
2177 lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
2178 conf1_write(lanai);
2181 if ((result = sram_test_and_clear(lanai)) != 0)
2184 /* 3.10: initialize lanai registers */
2185 lanai->conf1 |= CONFIG1_DMA_ENABLE;
2186 conf1_write(lanai);
2187 if ((result = service_buffer_allocate(lanai)) != 0)
2189 if ((result = vcc_table_allocate(lanai)) != 0)
2191 lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
2193 conf2_write(lanai);
2194 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
2195 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */
2196 if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,
2197 DEV_LABEL, lanai)) != 0) {
2202 intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
2204 lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
2207 conf1_write(lanai);
2208 lanai->status = reg_read(lanai, Status_Reg);
2211 lanai->conf1 |= CONFIG1_POWERDOWN;
2212 conf1_write(lanai);
2214 memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
2215 lanai_timed_poll_start(lanai);
2217 "(%pMF)\n", lanai->number, (int) lanai->pci->revision,
2218 lanai->base, lanai->pci->irq, atmdev->esi);
2220 "board_rev=%d\n", lanai->number,
2221 lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno,
2222 (unsigned int) lanai->serialno, lanai->board_rev);
2226 vcc_table_deallocate(lanai);
2228 service_buffer_deallocate(lanai);
2230 reset_board(lanai);
2232 lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
2233 conf1_write(lanai);
2235 iounmap(lanai->base);
2236 lanai->base = NULL;
2238 pci_disable_device(lanai->pci);
2248 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2249 if (lanai->base==NULL)
2252 lanai->number);
2253 lanai_timed_poll_stop(lanai);
2255 lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
2256 conf1_write(lanai);
2258 intr_disable(lanai, INT_ALL);
2259 free_irq(lanai->pci->irq, lanai);
2260 reset_board(lanai);
2262 lanai->conf1 |= CONFIG1_POWERDOWN;
2263 conf1_write(lanai);
2265 pci_disable_device(lanai->pci);
2266 vcc_table_deallocate(lanai);
2267 service_buffer_deallocate(lanai);
2268 iounmap(lanai->base);
2269 kfree(lanai);
2276 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2284 if (--lanai->naal0 <= 0)
2285 aal0_buffer_free(lanai);
2287 lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);
2291 if (atmvcc == lanai->cbrvcc) {
2293 lanai_cbr_shutdown(lanai);
2294 lanai->cbrvcc = NULL;
2296 lanai_shutdown_tx_vci(lanai, lvcc);
2297 lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);
2301 host_vcc_unbind(lanai, lvcc);
2311 struct lanai_dev *lanai;
2320 lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2321 result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);
2327 DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number,
2329 lvcc = lanai->vccs[vci];
2341 if (lanai->naal0 == 0)
2342 result = aal0_buffer_allocate(lanai);
2345 lanai, lvcc, &atmvcc->qos);
2355 lanai->naal0++;
2360 result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);
2365 APRINTK(lanai->cbrvcc == NULL,
2367 lanai->cbrvcc = atmvcc;
2370 host_vcc_bind(lanai, lvcc, vci);
2380 if (lanai->cbrvcc == atmvcc)
2381 lanai_cbr_setup(lanai);
2394 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2404 if (unlikely(lanai == NULL)) {
2405 DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
2413 vcc_tx_aal5(lanai, lvcc, skb);
2422 vcc_tx_aal0(lanai, lvcc, skb);
2444 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2450 atmdev->number, lanai->type==lanai2 ? "2" : "HB",
2451 (unsigned int) lanai->serialno,
2452 (unsigned int) lanai->magicno, lanai->num_vci);
2455 lanai->board_rev, (int) lanai->pci->revision);
2458 &lanai->eeprom[EEPROM_MAC]);
2461 "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
2462 (lanai->status & STATUS_LOCD) ? 1 : 0,
2463 (lanai->status & STATUS_LED) ? 1 : 0,
2464 (lanai->status & STATUS_GPIN) ? 1 : 0);
2467 "aal0_rx=%zu\n", lanai_buf_size(&lanai->service),
2468 lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
2470 get_statistics(lanai);
2473 lanai->stats.ovfl_trash, lanai->stats.vci_trash,
2474 lanai->stats.hec_err, lanai->stats.atm_ovfl);
2479 lanai->stats.pcierr_parity_detect,
2480 lanai->stats.pcierr_serr_set,
2481 lanai->stats.pcierr_m_target_abort);
2484 "master_parity=%u\n", lanai->stats.pcierr_s_target_abort,
2485 lanai->stats.pcierr_master_parity);
2488 "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx,
2489 lanai->stats.service_notx,
2490 lanai->stats.service_rxnotaal5);
2493 lanai->stats.dma_reenable, lanai->stats.card_reset);
2501 if ((lvcc = lanai->vccs[left]) != NULL)
2526 lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
2554 struct lanai_dev *lanai;
2558 lanai = kzalloc(sizeof(*lanai), GFP_KERNEL);
2559 if (lanai == NULL) {
2569 kfree(lanai);
2573 atmdev->dev_data = lanai;
2574 lanai->pci = pci;
2575 lanai->type = (enum lanai_type) ident->device;
2581 kfree(lanai);