Lines Matching defs:he_readl
177 #define he_readl(dev, reg) readl((dev)->membase + (reg))
186 (void) he_readl(he_dev, CON_DAT); /* flush posted writes */
188 while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
204 while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
205 return he_readl(he_dev, CON_DAT);
453 lbm_offset = he_readl(he_dev, RCMLBM_BA);
483 lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
513 lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
1058 status = he_readl(he_dev, RESET_CNTL);
1065 host_cntl = he_readl(he_dev, HOST_CNTL);
1096 lb_swap = he_readl(he_dev, LB_SWAP);
1497 reg = he_readl(he_dev, RC_CONFIG);
1548 reg = he_readl(he_dev, RC_CONFIG);
1888 RBPL_MASK(he_readl(he_dev, G0_RBPL_S)));
1976 hprintk("abort 0x%x\n", he_readl(he_dev, ABORT_ADDR));
2006 (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata; flush posted writes */
2029 ((he_readl(he_dev, IRQ0_BASE) & IRQ_MASK) << 2));
2030 (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata */
2042 (void) he_readl(he_dev, INT_FIFO); /* flush posted writes */
2071 TPDRQ_MASK(he_readl(he_dev, TPDRQ_B_H)));
2111 (void) he_readl(he_dev, TPDRQ_T); /* flush posted writes */
2354 while (he_readl(he_dev, RCC_STAT) & RCC_BUSY) {
2632 reg.val = he_readl(he_dev, reg.addr);
2679 (void) he_readl(he_dev, FRAMER + (addr*4)); /* flush posted writes */
2692 reg = he_readl(he_dev, FRAMER + (addr*4));
2725 mcc += he_readl(he_dev, MCC);
2726 oec += he_readl(he_dev, OEC);
2727 dcc += he_readl(he_dev, DCC);
2728 cec += he_readl(he_dev, CEC);
2753 rbpl_head = RBPL_MASK(he_readl(he_dev, G0_RBPL_S));
2754 rbpl_tail = RBPL_MASK(he_readl(he_dev, G0_RBPL_T));
2820 tmp_read = he_readl(he_dev, HOST_CNTL);