Lines Matching refs:mmio
419 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
428 mmio += PDC_CHIP0_OFS;
466 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
470 ata_port_dbg(ap, "ata pkt buf ofs %u, prd size %u, mmio copied\n",
478 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
484 mmio += PDC_CHIP0_OFS;
500 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
504 ata_port_dbg(ap, "ata pkt buf ofs %u, mmio copied\n", i);
529 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
532 mmio += PDC_CHIP0_OFS;
534 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
535 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
537 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
538 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
597 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
603 mmio += PDC_CHIP0_OFS;
620 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
621 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
658 void __iomem *mmio)
672 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
683 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
698 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
701 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
702 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
711 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
795 void __iomem *mmio = ap->ioaddr.cmd_addr;
800 tmp = readl(mmio + PDC_CTLSTAT);
803 writel(tmp, mmio + PDC_CTLSTAT);
804 readl(mmio + PDC_CTLSTAT); /* flush */
809 void __iomem *mmio = ap->ioaddr.cmd_addr;
818 tmp = readl(mmio + PDC_CTLSTAT);
820 writel(tmp, mmio + PDC_CTLSTAT);
821 readl(mmio + PDC_CTLSTAT); /* flush */
826 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
833 tmp = readl(mmio);
840 writel(tmp, mmio);
844 writel(tmp, mmio);
845 readl(mmio); /* flush */
943 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
947 mmio += PDC_CHIP0_OFS;
953 writel(0x01, mmio + PDC_GENERAL_CTLR);
954 readl(mmio + PDC_GENERAL_CTLR);
955 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
956 readl(mmio + PDC_DIMM_WINDOW_CTLR);
967 writel(0x01, mmio + PDC_GENERAL_CTLR);
968 readl(mmio + PDC_GENERAL_CTLR);
969 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
970 readl(mmio + PDC_DIMM_WINDOW_CTLR);
978 writel(0x01, mmio + PDC_GENERAL_CTLR);
979 readl(mmio + PDC_GENERAL_CTLR);
980 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
981 readl(mmio + PDC_DIMM_WINDOW_CTLR);
994 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
998 mmio += PDC_CHIP0_OFS;
1004 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1005 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1011 writel(0x01, mmio + PDC_GENERAL_CTLR);
1012 readl(mmio + PDC_GENERAL_CTLR);
1017 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1018 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1020 writel(0x01, mmio + PDC_GENERAL_CTLR);
1021 readl(mmio + PDC_GENERAL_CTLR);
1028 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1029 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1031 writel(0x01, mmio + PDC_GENERAL_CTLR);
1032 readl(mmio + PDC_GENERAL_CTLR);
1040 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1046 mmio += PDC_CHIP0_OFS;
1052 writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1053 readl(mmio + PDC_I2C_ADDR_DATA);
1057 mmio + PDC_I2C_CONTROL);
1060 status = readl(mmio + PDC_I2C_CONTROL);
1062 status = readl(mmio + PDC_I2C_ADDR_DATA);
1099 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1119 mmio += PDC_CHIP0_OFS;
1152 writel(data, mmio + PDC_DIMM0_CONTROL);
1153 readl(mmio + PDC_DIMM0_CONTROL);
1162 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1165 mmio += PDC_CHIP0_OFS;
1175 writel(data, mmio + PDC_SDRAM_CONTROL);
1176 readl(mmio + PDC_SDRAM_CONTROL);
1188 writel(data, mmio + PDC_SDRAM_CONTROL);
1189 readl(mmio + PDC_SDRAM_CONTROL);
1196 writel(data, mmio + PDC_SDRAM_CONTROL);
1200 data = readl(mmio + PDC_SDRAM_CONTROL);
1220 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1223 mmio += PDC_CHIP0_OFS;
1228 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1229 time_period = readl(mmio + PDC_TIME_PERIOD);
1233 writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1234 readl(mmio + PDC_TIME_CONTROL);
1244 tcount = readl(mmio + PDC_TIME_COUNTER);
1274 writel(pci_status, mmio + PDC_CTL_STATUS);
1275 readl(mmio + PDC_CTL_STATUS);
1359 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1362 mmio += PDC_CHIP0_OFS;
1367 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1369 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1374 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1376 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1377 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1381 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1383 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1384 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1426 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");