Lines Matching refs:base
148 void __iomem *base;
155 void __iomem *base = priv->base;
158 iowrite32(0, base + SATAPHYADDR_REG);
160 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
163 iowrite32(0, base + SATAPHYRESET_REG);
169 void __iomem *base = priv->base;
173 iowrite32(0, base + SATAPHYRESET_REG);
175 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
177 iowrite32(val, base + SATAPHYWDATA_REG);
182 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
185 val = ioread32(base + SATAPHYACK_REG);
192 iowrite32(0, base + SATAPHYADDR_REG);
208 void __iomem *base = priv->base;
210 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
211 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
212 iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
213 iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
215 RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG);
223 iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG);
231 void __iomem *base = priv->base;
234 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
239 iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
541 void __iomem *base = priv->base;
546 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
549 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
557 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
567 void __iomem *base = priv->base;
571 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
574 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
581 void __iomem *base = priv->base;
585 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
589 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
602 status = ioread32(priv->base + ATAPI_STATUS_REG);
657 serror = ioread32(priv->base + SCRSERR_REG);
699 void __iomem *base = priv->base;
707 sataintstat = ioread32(base + SATAINTSTAT_REG);
712 iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG);
734 void __iomem *base = priv->base;
744 ioaddr->cmd_addr = base + SDATA_REG;
745 ioaddr->ctl_addr = base + SSDEVCON_REG;
746 ioaddr->scr_addr = base + SCRSSTS_REG;
763 void __iomem *base = priv->base;
767 val = ioread32(base + ATAPI_CONTROL1_REG);
769 iowrite32(val, base + ATAPI_CONTROL1_REG);
772 val = ioread32(base + ATAPI_CONTROL1_REG);
776 iowrite32(val, base + ATAPI_CONTROL1_REG);
779 val = ioread32(base + ATAPI_CONTROL1_REG);
781 iowrite32(val, base + ATAPI_CONTROL1_REG);
784 iowrite32(0, base + SATAINTSTAT_REG);
785 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
788 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
889 priv->base = devm_platform_ioremap_resource(pdev, 0);
890 if (IS_ERR(priv->base)) {
891 ret = PTR_ERR(priv->base);
916 void __iomem *base = priv->base;
921 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
923 iowrite32(0, base + SATAINTSTAT_REG);
924 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
935 void __iomem *base = priv->base;
940 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
942 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
953 void __iomem *base = priv->base;
966 iowrite32(0, base + SATAINTSTAT_REG);
967 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
971 base + ATAPI_INT_ENABLE_REG);