Lines Matching defs:tmp
600 u16 tmp, status;
616 tmp = readw(mmio + NV_ADMA_CTL);
617 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
638 u16 tmp, status;
646 tmp = readw(mmio + NV_ADMA_CTL);
647 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
1016 u16 tmp;
1028 tmp = readw(mmio + NV_ADMA_CTL);
1029 writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
1038 u16 tmp;
1046 tmp = readw(mmio + NV_ADMA_CTL);
1047 writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
1102 u16 tmp;
1173 tmp = readw(mmio + NV_ADMA_CTL);
1174 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1177 tmp = readw(mmio + NV_ADMA_CTL);
1178 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1181 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1217 u16 tmp;
1233 tmp = readw(mmio + NV_ADMA_CTL);
1234 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1237 tmp = readw(mmio + NV_ADMA_CTL);
1238 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1241 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1631 u16 tmp;
1670 tmp = readw(mmio + NV_ADMA_CTL);
1671 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1674 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1810 u32 tmp;
1819 tmp = readl(mmio + NV_CTL_MCP55);
1820 tmp &= ~(NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ);
1821 writel(tmp, mmio + NV_CTL_MCP55);
1829 u32 tmp;
1838 tmp = readl(mmio + NV_CTL_MCP55);
1839 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1847 u32 tmp;
1858 tmp = readl(mmio + NV_CTL_MCP55);
1859 dev_dbg(&pdev->dev, "HOST_CTL:0x%X\n", tmp);
1860 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1863 tmp = readl(mmio + NV_INT_ENABLE_MCP55);
1864 dev_dbg(&pdev->dev, "HOST_ENABLE:0x%X\n", tmp);
1865 writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);