Lines Matching defs:tmp
1820 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1822 *cmdw = cpu_to_le16(tmp);
3088 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3089 tmp |= (1 << 0);
3090 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3105 u32 tmp;
3107 tmp = readl(phy_mmio + MV5_PHY_MODE);
3109 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3110 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3115 u32 tmp;
3121 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3122 tmp |= ~(1 << 0);
3123 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3131 u32 tmp;
3135 tmp = readl(phy_mmio + MV5_LTMODE);
3136 tmp |= (1 << 19);
3137 writel(tmp, phy_mmio + MV5_LTMODE);
3139 tmp = readl(phy_mmio + MV5_PHY_CTL);
3140 tmp &= ~0x3;
3141 tmp |= 0x1;
3142 writel(tmp, phy_mmio + MV5_PHY_CTL);
3145 tmp = readl(phy_mmio + MV5_PHY_MODE);
3146 tmp &= ~mask;
3147 tmp |= hpriv->signal[port].pre;
3148 tmp |= hpriv->signal[port].amps;
3149 writel(tmp, phy_mmio + MV5_PHY_MODE);
3183 u32 tmp;
3190 tmp = readl(hc_mmio + 0x20);
3191 tmp &= 0x1c1c1c1c;
3192 tmp |= 0x03030303;
3193 writel(tmp, hc_mmio + 0x20);
3219 u32 tmp;
3221 tmp = readl(mmio + MV_PCI_MODE);
3222 tmp &= 0xff00ffff;
3223 writel(tmp, mmio + MV_PCI_MODE);
3240 u32 tmp;
3244 tmp = readl(mmio + GPIO_PORT_CTL);
3245 tmp &= 0x3;
3246 tmp |= (1 << 5) | (1 << 6);
3247 writel(tmp, mmio + GPIO_PORT_CTL);
3318 u32 tmp;
3320 tmp = readl(mmio + RESET_CFG);
3321 if ((tmp & (1 << 0)) == 0) {
3328 tmp = readl(port_mmio + PHY_MODE2);
3330 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3331 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3427 u32 tmp;
3430 tmp = readl(port_mmio + PHY_MODE2);
3432 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3433 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */