Lines Matching defs:port
144 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
147 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
214 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
215 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
237 DMA_IRQ = (1 << 0), /* shift by port # */
239 DEV_IRQ = (1 << 8), /* shift by port # */
505 * We keep a local cache of a few frequently accessed port
578 unsigned int port);
605 unsigned int port);
615 unsigned int port);
632 void __iomem *mmio, unsigned int port);
866 static inline unsigned int mv_hc_from_port(unsigned int port)
868 return port >> MV_PORT_HC_SHIFT;
871 static inline unsigned int mv_hardport_from_port(unsigned int port)
873 return port & MV_PORT_MASK;
881 * port is the sole input, in range 0..7.
885 * Note that port and hardport may be the same variable in some cases.
887 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
889 shift = mv_hc_from_port(port) * HC_SHIFT; \
890 hardport = mv_hardport_from_port(port); \
900 unsigned int port)
902 return mv_hc_base(base, mv_hc_from_port(port));
905 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
907 return mv_hc_base_from_port(base, port) +
909 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
912 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
914 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
915 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
937 * mv_save_cached_regs - (re-)initialize cached port registers
938 * @ap: the port whose registers we are caching
940 * Initialize the local cache of port registers,
958 * mv_write_cached_reg - write to a cached port register
1028 * and the corresponding individual port DONE_IRQ bits.
1057 unsigned int shift, hardport, port = ap->port_no;
1060 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1155 * @pp: port private data
1293 num_ports = 8; /* should be benign for 4 port devs */
1296 "%s: All registers for port(s) %u-%u:\n", __func__,
1314 dev_dbg(&pdev->dev, "%s: EDMA regs (port %i):\n", __func__, p);
1316 dev_dbg(&pdev->dev, "%s: SATA regs (port %i):\n", __func__, p);
1406 * Gen-II does not support NCQ over a port multiplier
1450 * If the port is completely idle, then allow the new qc.
1456 * The port is operating in host queuing mode (EDMA) with NCQ
1549 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1577 unsigned int port;
1583 for (port = 0; port < hpriv->n_ports; port++) {
1584 struct ata_port *this_ap = host->ports[port];
1694 * Allocate and point to DMA memory, init port private memory,
1756 * Stop DMA, cleanup port memory.
1918 * @ap: port to stop
1948 * @ap: port for which to retrieve DMA status.
2193 * @ap: ATA port to fetch status from
2220 * @ap: ATA port to send a FIS
2251 /* Restore original port configuration */
2392 * port. Turn off EDMA so there won't be problems accessing
2439 * before we freeze the port entirely.
2509 * Set a port flag to prevent further I/O being enqueued.
2510 * Leave the EDMA running to drain outstanding commands from this port.
2623 * mv_err_intr - Handle error interrupts on the port
2628 * Also, if the port disabled DMA, update our cached copy to match.
2845 * so that we have a consistent view for this port,
2884 unsigned int handled = 0, port;
2890 for (port = 0; port < hpriv->n_ports; port++) {
2891 struct ata_port *ap = host->ports[port];
2894 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2899 if (hardport == 0) { /* first port on this hc ? */
2906 port += MV_PORTS_PER_HC - 1;
2925 if ((port + p) >= hpriv->n_ports)
2931 hc_mmio = mv_hc_base_from_port(mmio, port);
2936 * Handle interrupts signalled for this port:
3127 unsigned int port)
3129 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3147 tmp |= hpriv->signal[port].pre;
3148 tmp |= hpriv->signal[port].amps;
3156 unsigned int port)
3158 void __iomem *port_mmio = mv_port_base(mmio, port);
3160 mv_reset_channel(hpriv, mmio, port);
3201 unsigned int hc, port;
3204 for (port = 0; port < MV_PORTS_PER_HC; port++)
3206 (hc * MV_PORTS_PER_HC) + port);
3340 unsigned int port)
3342 void __iomem *port_mmio = mv_port_base(mmio, port);
3402 m2 |= hpriv->signal[port].amps;
3403 m2 |= hpriv->signal[port].pre;
3439 void __iomem *mmio, unsigned int port)
3441 void __iomem *port_mmio = mv_port_base(mmio, port);
3443 mv_reset_channel(hpriv, mmio, port);
3480 unsigned int port;
3482 for (port = 0; port < hpriv->n_ports; port++)
3483 mv_soc_reset_hc_port(hpriv, mmio, port);
3502 void __iomem *mmio, unsigned int port)
3504 void __iomem *port_mmio = mv_port_base(mmio, port);
3667 unsigned int port = ap->port_no;
3668 unsigned int hardport = mv_hardport_from_port(port);
3669 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3673 /* clear EDMA errors on this port */
3684 * mv_port_init - Perform some early initialization on a single port.
3685 * @port: libata data structure storing shadow register addresses
3686 * @port_mmio: base address of the port
3689 * interrupts on the port, and unmask interrupts for the future
3690 * start of the port.
3695 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3701 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3702 port->error_addr =
3703 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3704 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3705 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3706 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3707 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3708 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3709 port->status_addr =
3710 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3712 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3714 /* Clear any currently outstanding port interrupt conditions */
3912 * our port init and clear/unmask all/relevant host interrupts.
3919 int rc = 0, n_hc, port, hc;
3943 for (port = 0; port < host->n_ports; port++)
3945 hpriv->ops->read_preamp(hpriv, port, mmio);
3955 for (port = 0; port < host->n_ports; port++) {
3956 struct ata_port *ap = host->ports[port];
3957 void __iomem *port_mmio = mv_port_base(mmio, port);
3984 * The per-port interrupts get done later as ports are set up.
4053 int port;
4131 for (port = 0; port < n_ports; port++) {
4133 sprintf(port_number, "%d", port);
4134 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4135 if (!IS_ERR(hpriv->port_clks[port]))
4136 clk_prepare_enable(hpriv->port_clks[port]);
4138 sprintf(port_number, "port%d", port);
4139 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev,
4141 if (IS_ERR(hpriv->port_phys[port])) {
4142 rc = PTR_ERR(hpriv->port_phys[port]);
4143 hpriv->port_phys[port] = NULL;
4148 hpriv->n_ports = port;
4151 phy_power_on(hpriv->port_phys[port]);
4194 for (port = 0; port < hpriv->n_ports; port++) {
4195 if (!IS_ERR(hpriv->port_clks[port])) {
4196 clk_disable_unprepare(hpriv->port_clks[port]);
4197 clk_put(hpriv->port_clks[port]);
4199 phy_power_off(hpriv->port_phys[port]);
4217 int port;
4224 for (port = 0; port < host->n_ports; port++) {
4225 if (!IS_ERR(hpriv->port_clks[port])) {
4226 clk_disable_unprepare(hpriv->port_clks[port]);
4227 clk_put(hpriv->port_clks[port]);
4229 phy_power_off(hpriv->port_phys[port]);
4372 int n_ports, port, rc;
4410 for (port = 0; port < host->n_ports; port++) {
4411 struct ata_port *ap = host->ports[port];
4412 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4416 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");