Lines Matching refs:port
88 static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
91 return 1 << (3 * pdata->port_to_sgpio[port] + shift);
94 static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
97 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
100 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
103 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
106 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
109 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
112 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
170 /* save off new led state for port/slot */
329 int phy_count = 0, phy, port = 0, i;
340 "calxeda,port-phys", "#phy-cells",
341 port, &phy_data))
355 port_data[port].lane_mapping = phy_data.args[0];
357 port_data[port].phy_devs = tmp;
358 port_data[port].phy_base = cphy_base[phy];
360 port += 1;
361 } while (port < CPHY_PORT_COUNT);
363 tx_atten, port);
364 for (i = 0; i < port; i++)
515 * port, at other times, that of the last possible port, so
516 * determining the maximum port number requires looking at
540 ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
546 /* disabled/not-implemented port */