Lines Matching refs:sg
125 bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1)
127 if (!sg->sata_bridge)
133 if ((sg->muxmode == GEMINI_MUXMODE_2) &&
136 if ((sg->muxmode == GEMINI_MUXMODE_3) &&
144 enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg)
146 return sg->muxmode;
150 static int gemini_sata_setup_bridge(struct sata_gemini *sg,
160 if (sg->muxmode == GEMINI_MUXMODE_2)
162 writel(val, sg->base + GEMINI_SATA0_CTRL);
166 if (sg->muxmode == GEMINI_MUXMODE_3)
168 writel(val, sg->base + GEMINI_SATA1_CTRL);
179 val = readl(sg->base + GEMINI_SATA0_STATUS);
181 val = readl(sg->base + GEMINI_SATA1_STATUS);
188 dev_info(sg->dev, "SATA%d PHY %s\n", bridge,
194 int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge)
200 pclk = sg->sata0_pclk;
202 pclk = sg->sata1_pclk;
207 ret = gemini_sata_setup_bridge(sg, bridge);
215 void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge)
218 clk_disable(sg->sata0_pclk);
220 clk_disable(sg->sata1_pclk);
224 int gemini_sata_reset_bridge(struct sata_gemini *sg,
228 reset_control_reset(sg->sata0_reset);
230 reset_control_reset(sg->sata1_reset);
232 return gemini_sata_setup_bridge(sg, bridge);
236 static int gemini_sata_bridge_init(struct sata_gemini *sg)
238 struct device *dev = sg->dev;
242 sg->sata0_pclk = devm_clk_get(dev, "SATA0_PCLK");
243 if (IS_ERR(sg->sata0_pclk)) {
247 sg->sata1_pclk = devm_clk_get(dev, "SATA1_PCLK");
248 if (IS_ERR(sg->sata1_pclk)) {
253 ret = clk_prepare_enable(sg->sata0_pclk);
258 ret = clk_prepare_enable(sg->sata1_pclk);
261 clk_disable_unprepare(sg->sata0_pclk);
265 sg->sata0_reset = devm_reset_control_get_exclusive(dev, "sata0");
266 if (IS_ERR(sg->sata0_reset)) {
268 clk_disable_unprepare(sg->sata1_pclk);
269 clk_disable_unprepare(sg->sata0_pclk);
270 return PTR_ERR(sg->sata0_reset);
272 sg->sata1_reset = devm_reset_control_get_exclusive(dev, "sata1");
273 if (IS_ERR(sg->sata1_reset)) {
275 clk_disable_unprepare(sg->sata1_pclk);
276 clk_disable_unprepare(sg->sata0_pclk);
277 return PTR_ERR(sg->sata1_reset);
280 sata_id = readl(sg->base + GEMINI_SATA_ID);
281 sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID);
282 sg->sata_bridge = true;
283 clk_disable(sg->sata0_pclk);
284 clk_disable(sg->sata1_pclk);
318 struct sata_gemini *sg;
325 sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
326 if (!sg)
328 sg->dev = dev;
330 sg->base = devm_platform_ioremap_resource(pdev, 0);
331 if (IS_ERR(sg->base))
332 return PTR_ERR(sg->base);
342 ret = gemini_sata_bridge_init(sg);
348 sg->ide_pins = true;
350 if (!sg->sata_bridge && !sg->ide_pins) {
366 sg->muxmode = muxmode;
382 if (sg->ide_pins) {
389 platform_set_drvdata(pdev, sg);
390 sg_singleton = sg;
395 if (sg->sata_bridge) {
396 clk_unprepare(sg->sata1_pclk);
397 clk_unprepare(sg->sata0_pclk);
404 struct sata_gemini *sg = platform_get_drvdata(pdev);
406 if (sg->sata_bridge) {
407 clk_unprepare(sg->sata1_pclk);
408 clk_unprepare(sg->sata0_pclk);