Lines Matching refs:ioread32
319 hcr_base, ioread32(hcr_base + ICC));
356 rx_watermark = ioread32(csr_base + TRANSCFG);
380 temp = ioread32(csr_base + TRANSCFG);
399 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
548 ioread32(CQ + hcr_base),
549 ioread32(CA + hcr_base),
550 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
558 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
561 ioread32(CE + hcr_base),
562 ioread32(DE + hcr_base),
563 ioread32(CC + hcr_base),
564 ioread32(COMMANDSTAT + host_priv->csr_base));
626 *val = ioread32(ssr_base + (sc_reg * 4));
637 ioread32(CQ + hcr_base),
638 ioread32(CA + hcr_base),
639 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
641 ioread32(host_priv->csr_base + COMMANDSTAT));
644 temp = ioread32(hcr_base + HCONTROL);
648 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
658 temp = ioread32(hcr_base + HSTATUS);
666 temp = ioread32(hcr_base + HCONTROL);
670 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
679 temp = ioread32(hcr_base + HCONTROL);
689 temp = ioread32(hcr_base + HCONTROL);
694 temp = ioread32(hcr_base + HCONTROL);
746 temp = ioread32(hcr_base + HCONTROL);
749 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
750 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
751 ata_port_dbg(ap, "CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
767 temp = ioread32(hcr_base + HCONTROL);
789 temp = ioread32(hcr_base + SIGNATURE);
791 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
792 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
816 temp = ioread32(hcr_base + HCONTROL);
839 ioread32(hcr_base + HSTATUS),
840 ioread32(hcr_base + HCONTROL));
856 temp = ioread32(hcr_base + HCONTROL);
870 ioread32(hcr_base + HSTATUS),
871 ioread32(hcr_base + HCONTROL));
882 ioread32(hcr_base + HSTATUS));
960 ioread32(CQ + hcr_base),
961 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
973 ioread32(CQ + hcr_base),
974 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
979 ioread32(hcr_base + HSTATUS),
980 ioread32(hcr_base + HCONTROL),
1027 ata_port_dbg(ap, "ccreg = 0x%x\n", ioread32(hcr_base + CC));
1028 ata_port_dbg(ap, "cereg = 0x%x\n", ioread32(hcr_base + CE));
1064 hstatus = ioread32(hcr_base + HSTATUS);
1065 cereg = ioread32(hcr_base + CE);
1081 hstatus, cereg, ioread32(hcr_base + DE), SError);
1119 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1125 dereg = ioread32(hcr_base + DE);
1147 dereg = ioread32(hcr_base + DE);
1189 hstatus = ioread32(hcr_base + HSTATUS);
1194 done_mask = ioread32(hcr_base + CC);
1202 hcontrol = ioread32(hcr_base + HCONTROL);
1236 ioread32(hcr_base + CA),
1237 ioread32(hcr_base + CE),
1238 ioread32(hcr_base + CQ),
1247 done_mask, ioread32(hcr_base + CA),
1248 ioread32(hcr_base + CE));
1253 i, ioread32(hcr_base + CC),
1254 ioread32(hcr_base + CA));
1264 ioread32(hcr_base + CC));
1272 ioread32(hcr_base + CC));
1288 interrupt_enables = ioread32(hcr_base + HSTATUS);
1330 temp = ioread32(hcr_base + HCONTROL);
1334 temp = ioread32(hcr_base + HSTATUS);
1339 temp = ioread32(hcr_base + HCONTROL);
1343 dev_dbg(host->dev, "icc = 0x%x\n", ioread32(hcr_base + ICC));
1363 ioread32(hcr_base + HSTATUS), ioread32(hcr_base + HCONTROL));
1446 temp = ioread32(csr_base + TRANSCFG);
1452 ioread32(csr_base + TRANSCFG));
1567 iowrite32((ioread32(hcr_base + HCONTROL)