Lines Matching defs:hcr_base
282 void __iomem *hcr_base;
295 void __iomem *hcr_base = host_priv->hcr_base;
310 iowrite32((count << 24 | ticks), hcr_base + ICC);
319 hcr_base, ioread32(hcr_base + ICC));
390 void __iomem *hcr_base)
399 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
503 void __iomem *hcr_base = host_priv->hcr_base;
504 unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base);
544 void __iomem *hcr_base = host_priv->hcr_base;
545 unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base);
548 ioread32(CQ + hcr_base),
549 ioread32(CA + hcr_base),
550 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
552 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
555 iowrite32(1 << tag, CQ + hcr_base);
558 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
561 ioread32(CE + hcr_base),
562 ioread32(DE + hcr_base),
563 ioread32(CC + hcr_base),
573 void __iomem *hcr_base = host_priv->hcr_base;
574 unsigned int tag = sata_fsl_tag(qc->ap, qc->hw_tag, hcr_base);
633 void __iomem *hcr_base = host_priv->hcr_base;
637 ioread32(CQ + hcr_base),
638 ioread32(CA + hcr_base),
639 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
644 temp = ioread32(hcr_base + HCONTROL);
645 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
648 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
654 void __iomem *hcr_base = host_priv->hcr_base;
658 temp = ioread32(hcr_base + HSTATUS);
663 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
666 temp = ioread32(hcr_base + HCONTROL);
667 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
670 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
676 void __iomem *hcr_base = host_priv->hcr_base;
679 temp = ioread32(hcr_base + HCONTROL);
680 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
686 void __iomem *hcr_base = host_priv->hcr_base;
689 temp = ioread32(hcr_base + HCONTROL);
691 iowrite32(temp, hcr_base + HCONTROL);
694 temp = ioread32(hcr_base + HCONTROL);
695 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
706 void __iomem *hcr_base = host_priv->hcr_base;
736 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
746 temp = ioread32(hcr_base + HCONTROL);
747 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
749 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
750 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
751 ata_port_dbg(ap, "CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
761 void __iomem *hcr_base = host_priv->hcr_base;
767 temp = ioread32(hcr_base + HCONTROL);
770 iowrite32(temp, hcr_base + HCONTROL);
773 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
785 void __iomem *hcr_base = host_priv->hcr_base;
789 temp = ioread32(hcr_base + SIGNATURE);
791 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
792 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
807 void __iomem *hcr_base = host_priv->hcr_base;
816 temp = ioread32(hcr_base + HCONTROL);
818 iowrite32(temp, hcr_base + HCONTROL);
821 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
839 ioread32(hcr_base + HSTATUS),
840 ioread32(hcr_base + HCONTROL));
856 temp = ioread32(hcr_base + HCONTROL);
859 iowrite32(temp, hcr_base + HCONTROL);
861 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
870 ioread32(hcr_base + HSTATUS),
871 ioread32(hcr_base + HCONTROL));
879 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
882 ioread32(hcr_base + HSTATUS));
891 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
921 void __iomem *hcr_base = host_priv->hcr_base;
960 ioread32(CQ + hcr_base),
961 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
963 iowrite32(0xFFFF, CC + hcr_base);
965 iowrite32(pmp, CQPMP + hcr_base);
966 iowrite32(1, CQ + hcr_base);
968 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
973 ioread32(CQ + hcr_base),
974 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
979 ioread32(hcr_base + HSTATUS),
980 ioread32(hcr_base + HCONTROL),
1003 iowrite32(pmp, CQPMP + hcr_base);
1004 iowrite32(1, CQ + hcr_base);
1012 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1027 ata_port_dbg(ap, "ccreg = 0x%x\n", ioread32(hcr_base + CC));
1028 ata_port_dbg(ap, "cereg = 0x%x\n", ioread32(hcr_base + CE));
1056 void __iomem *hcr_base = host_priv->hcr_base;
1064 hstatus = ioread32(hcr_base + HSTATUS);
1065 cereg = ioread32(hcr_base + CE);
1081 hstatus, cereg, ioread32(hcr_base + DE), SError);
1119 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1125 dereg = ioread32(hcr_base + DE);
1126 iowrite32(dereg, hcr_base + DE);
1127 iowrite32(cereg, hcr_base + CE);
1147 dereg = ioread32(hcr_base + DE);
1148 iowrite32(dereg, hcr_base + DE);
1149 iowrite32(cereg, hcr_base + CE);
1182 void __iomem *hcr_base = host_priv->hcr_base;
1189 hstatus = ioread32(hcr_base + HSTATUS);
1194 done_mask = ioread32(hcr_base + CC);
1202 hcontrol = ioread32(hcr_base + HCONTROL);
1204 hcr_base + HCONTROL);
1208 hcr_base + HCONTROL);
1236 ioread32(hcr_base + CA),
1237 ioread32(hcr_base + CE),
1238 ioread32(hcr_base + CQ),
1244 iowrite32(done_mask, hcr_base + CC);
1247 done_mask, ioread32(hcr_base + CA),
1248 ioread32(hcr_base + CE));
1253 i, ioread32(hcr_base + CC),
1254 ioread32(hcr_base + CA));
1260 iowrite32(1, hcr_base + CC);
1264 ioread32(hcr_base + CC));
1272 ioread32(hcr_base + CC));
1273 iowrite32(done_mask, hcr_base + CC);
1282 void __iomem *hcr_base = host_priv->hcr_base;
1288 interrupt_enables = ioread32(hcr_base + HSTATUS);
1305 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1320 void __iomem *hcr_base = host_priv->hcr_base;
1330 temp = ioread32(hcr_base + HCONTROL);
1331 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1334 temp = ioread32(hcr_base + HSTATUS);
1336 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1339 temp = ioread32(hcr_base + HCONTROL);
1340 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1343 dev_dbg(host->dev, "icc = 0x%x\n", ioread32(hcr_base + ICC));
1344 iowrite32(0x01000000, hcr_base + ICC);
1347 iowrite32(0x00000FFFF, hcr_base + CE);
1348 iowrite32(0x00000FFFF, hcr_base + DE);
1363 ioread32(hcr_base + HSTATUS), ioread32(hcr_base + HCONTROL));
1372 iounmap(host_priv->hcr_base);
1425 void __iomem *hcr_base = NULL;
1438 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1439 if (!hcr_base)
1442 ssr_base = hcr_base + 0x100;
1443 csr_base = hcr_base + 0x140;
1458 host_priv->hcr_base = hcr_base;
1522 if (hcr_base)
1523 iounmap(hcr_base);
1554 void __iomem *hcr_base = host_priv->hcr_base;
1565 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1567 iowrite32((ioread32(hcr_base + HCONTROL)
1571 hcr_base + HCONTROL);