Lines Matching refs:pi
32 static int frpw_read_regr(struct pi_adapter *pi, int cont, int regr)
47 static void frpw_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
56 static void frpw_read_block_int(struct pi_adapter *pi, char *buf, int count,
61 switch (pi->mode) {
126 static void frpw_read_block(struct pi_adapter *pi, char *buf, int count)
128 frpw_read_block_int(pi, buf, count, 0x08);
131 static void frpw_write_block(struct pi_adapter *pi, char *buf, int count)
135 switch (pi->mode) {
170 static void frpw_connect(struct pi_adapter *pi)
172 pi->saved_r0 = r0();
173 pi->saved_r2 = r2();
177 static void frpw_disconnect(struct pi_adapter *pi)
180 w0(pi->saved_r0);
181 w2(pi->saved_r2);
189 static int frpw_test_pnp(struct pi_adapter *pi)
198 olddelay = pi->delay;
199 pi->delay = 10;
201 pi->saved_r0 = r0();
202 pi->saved_r2 = r2();
208 pi->delay = olddelay;
209 w0(pi->saved_r0);
210 w2(pi->saved_r2);
216 * We use the pi->private to remember the result of the PNP test.
219 static int frpw_test_proto(struct pi_adapter *pi)
225 if ((pi->private >> 1) != pi->port)
226 pi->private = frpw_test_pnp(pi) + 2*pi->port;
228 if (((pi->private & 0x1) == 0) && (pi->mode > 2)) {
229 dev_dbg(&pi->dev,
230 "frpw: Xilinx does not support mode %d\n", pi->mode);
234 if (((pi->private & 0x1) == 1) && (pi->mode == 2)) {
235 dev_dbg(&pi->dev, "frpw: ASIC does not support mode 2\n");
239 frpw_connect(pi);
241 frpw_write_regr(pi, 0, 6, 0xa0 + j * 0x10);
243 frpw_write_regr(pi, 0, 2, k ^ 0xaa);
244 frpw_write_regr(pi, 0, 3, k ^ 0x55);
245 if (frpw_read_regr(pi, 0, 2) != (k ^ 0xaa))
249 frpw_disconnect(pi);
251 frpw_connect(pi);
252 frpw_read_block_int(pi, scratch, 512, 0x10);
258 frpw_disconnect(pi);
260 dev_dbg(&pi->dev,
262 pi->port, (pi->private%2), pi->mode, e[0], e[1], r);
267 static void frpw_log_adapter(struct pi_adapter *pi)
272 dev_info(&pi->dev,
274 ((pi->private & 0x1) == 0) ? "Xilinx" : "ASIC",
275 pi->port, pi->mode, mode[pi->mode], pi->delay);