Lines Matching refs:cf_port
128 struct octeon_cf_port *cf_port = ap->private_data;
167 octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
168 if (cf_port->is_true_ide)
170 octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
175 reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
204 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
205 if (cf_port->is_true_ide)
207 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
213 struct octeon_cf_port *cf_port = ap->private_data;
249 c = (cf_port->dma_base & 8) >> 3;
279 cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
520 struct octeon_cf_port *cf_port;
522 cf_port = ap->private_data;
525 cf_port->dma_finished = 0;
536 struct octeon_cf_port *cf_port = qc->ap->private_data;
550 cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
553 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
581 cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
594 struct octeon_cf_port *cf_port = ap->private_data;
604 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
614 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
618 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
622 cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
641 struct octeon_cf_port *cf_port;
656 cf_port = ap->private_data;
658 dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
659 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
674 cf_port->dma_finished = 1;
677 if (!cf_port->dma_finished)
690 cvmx_write_csr(cf_port->dma_base + DMA_INT,
692 hrtimer_start_range_ns(&cf_port->delayed_finish,
707 struct octeon_cf_port *cf_port = container_of(hrt,
710 struct ata_port *ap = cf_port->ap;
724 if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)
817 struct octeon_cf_port *cf_port;
825 cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);
826 if (!cf_port)
829 cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");
839 cf_port->cs0 = upper_32_bits(reg);
841 if (cf_port->is_true_ide) {
857 cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start,
859 if (!cf_port->dma_base) {
886 cf_port->cs1 = upper_32_bits(reg);
904 ap->private_data = cf_port;
905 pdev->dev.platform_data = cf_port;
906 cf_port->ap = ap;
919 } else if (cf_port->is_true_ide) {
939 hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
941 cf_port->delayed_finish.function = octeon_cf_delayed_finish;
958 cf_port->c0 = ap->ioaddr.ctl_addr;
968 cf_port->is_true_ide ? ", True IDE" : "");
979 struct octeon_cf_port *cf_port = dev_get_platdata(dev);
981 if (cf_port->dma_base) {
985 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
989 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
993 cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
995 __raw_writeb(0, cf_port->c0);
997 __raw_writeb(ATA_SRST, cf_port->c0);
999 __raw_writeb(0, cf_port->c0);