Lines Matching defs:timing
144 unsigned long timing;
392 /* Get the timing data in cycles. For now play safe at 50Mhz */
426 /* Get the timing data in cycles. For now play safe at 50Mhz */
502 /* Get the timing data in cycles */
505 /* Setup timing is shared */
517 /* Select the right timing bank for write timing */
537 /* Ensure the timing register mode is right */
581 /* Get the timing data in cycles */
584 /* Setup timing is shared */
596 /* Select the right timing bank for write timing */
616 /* Ensure the timing register mode is right */
635 * MVB has a single set of timing registers and these are shared
670 * avoid the requirement to clock switch. We also have to load the timing
682 u8 timing;
684 /* Get the timing data in cycles */
694 timing = (recovery << 4) | active | 0x08;
695 ld_qdi->clock[adev->devno] = timing;
698 outb(timing, ld_qdi->timing + 2 * adev->devno);
700 outb(timing, ld_qdi->timing + 2 * ap->port_no);
704 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
724 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
767 ld->timing = lp->private;
821 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
823 reg = winbond_readcfg(ld_winbond->timing, 0x81);
825 /* Get the timing data in cycles */
833 timing = (active << 4) | recovery;
834 winbond_writecfg(ld_winbond->timing, timing, reg);
836 /* Load the setup timing */
844 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
852 ld->timing = lp->private;
910 reg |= 0xF0; /* programmable timing */