Lines Matching defs:timreg
148 u8 timreg;
172 timreg = udma_66_setup_time[i] << 4 |
175 timreg = udma_50_setup_time[i] << 4 |
181 timreg |= FTIDE010_UDMA_TIMING_MODE_56;
183 dev_dbg(ftide->dev, "UDMA write clkreg = %02x, timreg = %02x\n",
184 clkreg, timreg);
187 writeb(timreg, ftide->base + FTIDE010_UDMA_TIMING0 + devno);
195 timreg = mwdma_66_active_time[i] << 4 |
198 timreg = mwdma_50_active_time[i] << 4 |
202 "MWDMA write clkreg = %02x, timreg = %02x\n",
203 clkreg, timreg);
206 writeb(timreg, ftide->base + FTIDE010_MWDMA_TIMING);