Lines Matching refs:vbase
195 void __iomem *vbase;
231 dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS));
232 dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS));
233 dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN));
234 dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE));
235 dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG));
236 dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG));
237 dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR));
238 dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS));
239 dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN));
240 dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN));
248 writel(enable, acdev->vbase + GIRQ_STS_EN);
249 writel(enable, acdev->vbase + GIRQ_SGN_EN);
256 u32 val = readl(acdev->vbase + IRQ_EN);
259 writel(mask, acdev->vbase + IRQ_STS);
260 writel(val | mask, acdev->vbase + IRQ_EN);
262 writel(val & ~mask, acdev->vbase + IRQ_EN);
267 u32 val = readl(acdev->vbase + OP_MODE);
269 writel(val | CARD_RESET, acdev->vbase + OP_MODE);
271 writel(val & ~CARD_RESET, acdev->vbase + OP_MODE);
276 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
277 acdev->vbase + OP_MODE);
278 writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB,
279 acdev->vbase + OP_MODE);
286 u32 val = readl(acdev->vbase + CFI_STS);
333 writel(if_clk, acdev->vbase + CLK_CFG);
335 writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
351 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
352 acdev->vbase + OP_MODE);
458 xfer_ctr = readl(acdev->vbase + XFER_CTR) &
461 acdev->vbase + XFER_CTR);
500 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
501 acdev->vbase + XFER_CTR);
600 irqsts = readl(acdev->vbase + GIRQ_STS);
605 irqsts = readl(acdev->vbase + IRQ_STS);
606 writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */
607 writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */
620 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
621 acdev->vbase + XFER_CTR);
651 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
652 acdev->vbase + XFER_CTR);
679 u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK;
683 writel(xfer_ctr, acdev->vbase + XFER_CTR);
739 val = readl(acdev->vbase + OP_MODE) &
741 writel(val, acdev->vbase + OP_MODE);
742 val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK;
744 writel(val, acdev->vbase + TM_CFG);
758 opmode = readl(acdev->vbase + OP_MODE) &
760 tmcfg = readl(acdev->vbase + TM_CFG);
777 writel(opmode, acdev->vbase + OP_MODE);
778 writel(tmcfg, acdev->vbase + TM_CFG);
779 writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR);
840 acdev->vbase = devm_ioremap(&pdev->dev, res->start,
842 if (!acdev->vbase) {
887 ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT;
888 ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT;
889 ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR;
890 ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR;
891 ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC;
892 ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN;
893 ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL;
894 ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH;
895 ap->ioaddr.device_addr = acdev->vbase + ATA_SH;
896 ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD;
897 ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD;
898 ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR;
899 ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR;
902 (unsigned long long) res->start, acdev->vbase);