Lines Matching refs:at
40 * the ports at different locations).
52 struct ata_timing at, apeer;
62 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
71 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
74 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
77 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
78 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
86 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
91 ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
95 ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
99 t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
103 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
107 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
111 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
119 if (at.udma)
172 * on the bus at this point in time. We need to turn the post write buffer
302 /* If PIO or DMA isn't configured at all, don't limit. Let EH