Lines Matching defs:port_mmio
295 void __iomem *port_mmio = ahci_port_base(ap);
299 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
449 void __iomem *port_mmio;
588 port_mmio = __ahci_port_base(hpriv, i);
590 readl(port_mmio + PORT_CMD) & PORT_CMD_CAP;
624 void __iomem *port_mmio;
634 port_mmio = __ahci_port_base(hpriv, i);
635 writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD);
658 void __iomem *port_mmio = ahci_port_base(link->ap);
662 *val = readl(port_mmio + offset);
670 void __iomem *port_mmio = ahci_port_base(link->ap);
674 writel(val, port_mmio + offset);
682 void __iomem *port_mmio = ahci_port_base(ap);
686 tmp = readl(port_mmio + PORT_CMD);
688 writel(tmp, port_mmio + PORT_CMD);
689 readl(port_mmio + PORT_CMD); /* flush */
695 void __iomem *port_mmio = ahci_port_base(ap);
712 tmp = readl(port_mmio + PORT_CMD);
730 writel(tmp, port_mmio + PORT_CMD);
733 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
744 void __iomem *port_mmio = ahci_port_base(ap);
752 port_mmio + PORT_LST_ADDR_HI);
753 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
757 port_mmio + PORT_FIS_ADDR_HI);
758 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
761 tmp = readl(port_mmio + PORT_CMD);
763 writel(tmp, port_mmio + PORT_CMD);
766 readl(port_mmio + PORT_CMD);
772 void __iomem *port_mmio = ahci_port_base(ap);
776 tmp = readl(port_mmio + PORT_CMD);
778 writel(tmp, port_mmio + PORT_CMD);
781 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
792 void __iomem *port_mmio = ahci_port_base(ap);
795 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
800 writel(cmd, port_mmio + PORT_CMD);
804 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
813 void __iomem *port_mmio = ahci_port_base(ap);
825 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
831 u32 cmd = readl(port_mmio + PORT_CMD);
838 writel(cmd, port_mmio + PORT_CMD);
839 readl(port_mmio + PORT_CMD);
854 writel(cmd, port_mmio + PORT_CMD);
874 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
884 void __iomem *port_mmio = ahci_port_base(ap);
891 scontrol = readl(port_mmio + PORT_SCR_CTL);
893 writel(scontrol, port_mmio + PORT_SCR_CTL);
896 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
898 writel(cmd, port_mmio + PORT_CMD);
1262 void __iomem *port_mmio = ahci_port_base(ap);
1266 tmp = readl(port_mmio + PORT_SCR_ERR);
1268 writel(tmp, port_mmio + PORT_SCR_ERR);
1271 tmp = readl(port_mmio + PORT_IRQ_STAT);
1274 writel(tmp, port_mmio + PORT_IRQ_STAT);
1281 void __iomem *port_mmio)
1296 tmp = readl(port_mmio + PORT_CMD);
1306 void __iomem *port_mmio;
1312 port_mmio = ahci_port_base(ap);
1316 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1340 void __iomem *port_mmio = ahci_port_base(ap);
1344 tmp = readl(port_mmio + PORT_SIG);
1370 void __iomem *port_mmio = ahci_port_base(ap);
1372 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1396 tmp = readl(port_mmio + PORT_CMD);
1398 writel(tmp, port_mmio + PORT_CMD);
1401 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1419 void __iomem *port_mmio = ahci_port_base(ap);
1429 tmp = readl(port_mmio + PORT_FBS);
1432 writel(tmp, port_mmio + PORT_FBS);
1437 writel(1, port_mmio + PORT_CMD_ISSUE);
1440 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1447 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1534 void __iomem *port_mmio = ahci_port_base(link->ap);
1535 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1552 void __iomem *port_mmio = ahci_port_base(link->ap);
1553 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1554 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1570 void __iomem *port_mmio = ahci_port_base(ap);
1584 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1640 void __iomem *port_mmio = ahci_port_base(ap);
1646 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1652 writel(new_tmp, port_mmio + PORT_CMD);
1653 readl(port_mmio + PORT_CMD); /* flush */
1732 void __iomem *port_mmio = ahci_port_base(ap);
1733 u32 fbs = readl(port_mmio + PORT_FBS);
1741 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1742 fbs = readl(port_mmio + PORT_FBS);
1745 fbs = readl(port_mmio + PORT_FBS);
1765 void __iomem *port_mmio = ahci_port_base(ap);
1766 u32 fbs = readl(port_mmio + PORT_FBS);
1863 static void ahci_qc_complete(struct ata_port *ap, void __iomem *port_mmio)
1877 qc_active = readl(port_mmio + PORT_SCR_ACT);
1878 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1883 qc_active = readl(port_mmio + PORT_SCR_ACT);
1885 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1897 void __iomem *port_mmio, u32 status)
1917 ahci_qc_complete(ap, port_mmio);
1955 ahci_qc_complete(ap, port_mmio);
1960 void __iomem *port_mmio = ahci_port_base(ap);
1963 status = readl(port_mmio + PORT_IRQ_STAT);
1964 writel(status, port_mmio + PORT_IRQ_STAT);
1966 ahci_handle_port_interrupt(ap, port_mmio, status);
1972 void __iomem *port_mmio = ahci_port_base(ap);
1975 status = readl(port_mmio + PORT_IRQ_STAT);
1976 writel(status, port_mmio + PORT_IRQ_STAT);
1979 ahci_handle_port_interrupt(ap, port_mmio, status);
2052 void __iomem *port_mmio = ahci_port_base(ap);
2062 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2065 u32 fbs = readl(port_mmio + PORT_FBS);
2068 writel(fbs, port_mmio + PORT_FBS);
2072 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2200 void __iomem *port_mmio = ahci_port_base(ap);
2203 writel(0, port_mmio + PORT_IRQ_MASK);
2210 void __iomem *port_mmio = ahci_port_base(ap);
2215 tmp = readl(port_mmio + PORT_IRQ_STAT);
2216 writel(tmp, port_mmio + PORT_IRQ_STAT);
2220 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2252 void __iomem *port_mmio = ahci_port_base(ap);
2258 devslp = readl(port_mmio + PORT_DEVSLP);
2268 port_mmio + PORT_DEVSLP);
2317 writel(devslp, port_mmio + PORT_DEVSLP);
2333 void __iomem *port_mmio = ahci_port_base(ap);
2340 fbs = readl(port_mmio + PORT_FBS);
2351 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2352 fbs = readl(port_mmio + PORT_FBS);
2367 void __iomem *port_mmio = ahci_port_base(ap);
2374 fbs = readl(port_mmio + PORT_FBS);
2384 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2385 fbs = readl(port_mmio + PORT_FBS);
2398 void __iomem *port_mmio = ahci_port_base(ap);
2402 cmd = readl(port_mmio + PORT_CMD);
2404 writel(cmd, port_mmio + PORT_CMD);
2419 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2424 void __iomem *port_mmio = ahci_port_base(ap);
2430 cmd = readl(port_mmio + PORT_CMD);
2432 writel(cmd, port_mmio + PORT_CMD);
2438 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2460 void __iomem *port_mmio = ahci_port_base(ap);
2465 devslp = readl(port_mmio + PORT_DEVSLP);
2516 void __iomem *port_mmio = ahci_port_base(ap);
2517 u32 cmd = readl(port_mmio + PORT_CMD);