Lines Matching refs:ctx
91 static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
93 dev_dbg(ctx->dev, "Release memory from shutdown\n");
94 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
95 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
97 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
98 dev_err(ctx->dev, "failed to release memory from shutdown\n");
192 struct xgene_ahci_context *ctx = hpriv->plat_data;
201 if (ctx->class[ap->port_no] == ATA_DEV_PMP) {
208 if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) ||
209 (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET) ||
210 (ctx->last_cmd[ap->port_no] == ATA_CMD_SMART)))
216 ctx->last_cmd[ap->port_no] = qc->tf.command;
221 static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
223 void __iomem *diagcsr = ctx->csr_diag;
266 static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
268 void __iomem *mmio = ctx->hpriv->mmio;
271 dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
355 struct xgene_ahci_context *ctx = hpriv->plat_data;
374 dev_warn(ctx->dev, "link has error\n");
500 struct xgene_ahci_context *ctx = hpriv->plat_data;
522 ctx->class[ap->port_no] = *class;
648 struct xgene_ahci_context *ctx = hpriv->plat_data;
654 rc = xgene_ahci_init_memram(ctx);
659 xgene_ahci_set_phy_cfg(ctx, i);
664 writel(0, ctx->csr_core + INTSTATUSMASK);
665 val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
666 dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
669 writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
670 readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
671 writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
672 readl(ctx->csr_axi + INT_SLV_TMOMASK);
675 writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
676 writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
677 writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
678 writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
681 val = readl(ctx->csr_core + BUSCTLREG);
684 writel(val, ctx->csr_core + BUSCTLREG);
686 val = readl(ctx->csr_core + IOFMSTRWAUX);
689 writel(val, ctx->csr_core + IOFMSTRWAUX);
690 val = readl(ctx->csr_core + IOFMSTRWAUX);
691 dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
697 static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
702 if (!ctx->csr_mux)
705 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
707 writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
708 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
736 struct xgene_ahci_context *ctx;
748 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
749 if (!ctx)
752 hpriv->plat_data = ctx;
753 ctx->hpriv = hpriv;
754 ctx->dev = dev;
757 ctx->csr_core = devm_platform_ioremap_resource(pdev, 1);
758 if (IS_ERR(ctx->csr_core))
759 return PTR_ERR(ctx->csr_core);
762 ctx->csr_diag = devm_platform_ioremap_resource(pdev, 2);
763 if (IS_ERR(ctx->csr_diag))
764 return PTR_ERR(ctx->csr_diag);
767 ctx->csr_axi = devm_platform_ioremap_resource(pdev, 3);
768 if (IS_ERR(ctx->csr_axi))
769 return PTR_ERR(ctx->csr_axi);
778 ctx->csr_mux = csr;
812 dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
816 if ((rc = xgene_ahci_mux_select(ctx))) {
821 if (xgene_ahci_is_memram_inited(ctx)) {