Lines Matching refs:HOST_IRQ_STAT
540 * @irq_masked: HOST_IRQ_STAT value
543 * the HOST_IRQ_STAT register misses the edge interrupt
544 * when clearing of HOST_IRQ_STAT register and hardware
549 * 1. Read HOST_IRQ_STAT register and save the state.
550 * 2. Clear the HOST_IRQ_STAT register.
551 * 3. Read back the HOST_IRQ_STAT register.
552 * 4. If HOST_IRQ_STAT register equals to zero, then
557 * then update the state of HOST_IRQ_STAT saved in step 1.
568 if (!readl(hpriv->mmio + HOST_IRQ_STAT)) {
594 irq_stat = readl(mmio + HOST_IRQ_STAT);
603 * HOST_IRQ_STAT behaves as edge triggered latch meaning that
606 writel(irq_stat, mmio + HOST_IRQ_STAT);
662 writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
663 readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */