Lines Matching refs:tegra
20 #include <soc/tegra/fuse.h>
21 #include <soc/tegra/pmc.h>
25 #define DRV_NAME "tegra-ahci"
184 struct tegra_ahci_priv *tegra = hpriv->plat_data;
187 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) {
188 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
190 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
196 struct tegra_ahci_priv *tegra = hpriv->plat_data;
208 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
210 val = readl(tegra->sata_regs +
216 writel(val, tegra->sata_regs + SCFG_OFFSET +
219 val = readl(tegra->sata_regs +
225 writel(val, tegra->sata_regs + SCFG_OFFSET +
229 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
231 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
233 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
240 struct tegra_ahci_priv *tegra = hpriv->plat_data;
243 ret = regulator_bulk_enable(tegra->soc->num_supplies,
244 tegra->supplies);
248 if (!tegra->pdev->dev.pm_domain) {
250 tegra->sata_clk,
251 tegra->sata_rst);
256 reset_control_assert(tegra->sata_oob_rst);
257 reset_control_assert(tegra->sata_cold_rst);
263 reset_control_deassert(tegra->sata_cold_rst);
264 reset_control_deassert(tegra->sata_oob_rst);
269 clk_disable_unprepare(tegra->sata_clk);
271 if (!tegra->pdev->dev.pm_domain)
275 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
282 struct tegra_ahci_priv *tegra = hpriv->plat_data;
286 reset_control_assert(tegra->sata_rst);
287 reset_control_assert(tegra->sata_oob_rst);
288 reset_control_assert(tegra->sata_cold_rst);
290 clk_disable_unprepare(tegra->sata_clk);
291 if (!tegra->pdev->dev.pm_domain)
294 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
299 struct tegra_ahci_priv *tegra = hpriv->plat_data;
305 dev_err(&tegra->pdev->dev,
314 val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
317 writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
320 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
322 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
326 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
328 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
330 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
332 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
336 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
339 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
341 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
342 val &= ~(tegra->soc->regs->nvoob_comma_cnt_mask |
345 val |= (tegra->soc->regs->nvoob_comma_cnt_val |
348 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
353 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
356 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
358 if (tegra->soc->ops && tegra->soc->ops->init)
359 tegra->soc->ops->init(hpriv);
365 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
368 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
370 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
373 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
375 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
377 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
382 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
384 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
386 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
389 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
394 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
400 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
403 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
406 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
408 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
411 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
414 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
416 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
422 val = readl(tegra->sata_regs + SATA_INTR_MASK);
424 writel(val, tegra->sata_regs + SATA_INTR_MASK);
516 struct tegra_ahci_priv *tegra;
524 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
525 if (!tegra)
528 hpriv->plat_data = tegra;
530 tegra->pdev = pdev;
531 tegra->soc = of_device_get_match_data(&pdev->dev);
533 tegra->sata_regs = devm_platform_ioremap_resource(pdev, 1);
534 if (IS_ERR(tegra->sata_regs))
535 return PTR_ERR(tegra->sata_regs);
542 tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
543 if (IS_ERR(tegra->sata_aux_regs))
544 return PTR_ERR(tegra->sata_aux_regs);
547 tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
548 if (IS_ERR(tegra->sata_rst)) {
550 return PTR_ERR(tegra->sata_rst);
553 if (tegra->soc->has_sata_oob_rst) {
554 tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev,
556 if (IS_ERR(tegra->sata_oob_rst)) {
558 return PTR_ERR(tegra->sata_oob_rst);
562 tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
563 if (IS_ERR(tegra->sata_cold_rst)) {
565 return PTR_ERR(tegra->sata_cold_rst);
568 tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
569 if (IS_ERR(tegra->sata_clk)) {
571 return PTR_ERR(tegra->sata_clk);
574 tegra->supplies = devm_kcalloc(&pdev->dev,
575 tegra->soc->num_supplies,
576 sizeof(*tegra->supplies), GFP_KERNEL);
577 if (!tegra->supplies)
580 regulator_bulk_set_supply_names(tegra->supplies,
581 tegra->soc->supply_names,
582 tegra->soc->num_supplies);
585 tegra->soc->num_supplies,
586 tegra->supplies);