Lines Matching refs:mmu
279 struct ivpu_mmu_info *mmu = vdev->mmu;
280 struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab;
294 struct ivpu_mmu_info *mmu = vdev->mmu;
295 struct ivpu_mmu_strtab *strtab = &mmu->strtab;
314 struct ivpu_mmu_info *mmu = vdev->mmu;
315 struct ivpu_mmu_queue *q = &mmu->cmdq;
333 struct ivpu_mmu_info *mmu = vdev->mmu;
334 struct ivpu_mmu_queue *q = &mmu->evtq;
408 struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq;
416 struct ivpu_mmu_queue *q = &vdev->mmu->cmdq;
436 struct ivpu_mmu_queue *q = &vdev->mmu->cmdq;
484 struct ivpu_mmu_info *mmu = vdev->mmu;
488 memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE);
489 clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE);
490 mmu->cmdq.prod = 0;
491 mmu->cmdq.cons = 0;
493 memset(mmu->evtq.base, 0, IVPU_MMU_EVTQ_SIZE);
494 mmu->evtq.prod = 0;
495 mmu->evtq.cons = 0;
509 REGV_WR64(VPU_37XX_HOST_MMU_STRTAB_BASE, mmu->strtab.dma_q);
510 REGV_WR32(VPU_37XX_HOST_MMU_STRTAB_BASE_CFG, mmu->strtab.base_cfg);
512 REGV_WR64(VPU_37XX_HOST_MMU_CMDQ_BASE, mmu->cmdq.dma_q);
533 REGV_WR64(VPU_37XX_HOST_MMU_EVTQ_BASE, mmu->evtq.dma_q);
557 struct ivpu_mmu_info *mmu = vdev->mmu;
558 struct ivpu_mmu_strtab *strtab = &mmu->strtab;
559 struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab;
598 struct ivpu_mmu_info *mmu = vdev->mmu;
601 mutex_lock(&mmu->lock);
602 if (!mmu->on)
611 mutex_unlock(&mmu->lock);
617 struct ivpu_mmu_info *mmu = vdev->mmu;
618 struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab;
662 mutex_lock(&mmu->lock);
663 if (!mmu->on)
672 mutex_unlock(&mmu->lock);
705 struct ivpu_mmu_info *mmu = vdev->mmu;
710 drmm_mutex_init(&vdev->drm, &mmu->lock);
742 struct ivpu_mmu_info *mmu = vdev->mmu;
745 mutex_lock(&mmu->lock);
747 mmu->on = true;
767 mutex_unlock(&mmu->lock);
771 mmu->on = false;
772 mutex_unlock(&mmu->lock);
778 struct ivpu_mmu_info *mmu = vdev->mmu;
780 mutex_lock(&mmu->lock);
781 mmu->on = false;
782 mutex_unlock(&mmu->lock);
799 struct ivpu_mmu_queue *evtq = &vdev->mmu->evtq;