Lines Matching refs:dma_q
303 strtab->dma_q = IVPU_MMU_STRTAB_BASE_RA;
304 strtab->dma_q |= strtab->dma & IVPU_MMU_STRTAB_BASE_ADDR_MASK;
306 ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n",
307 &strtab->dma, &strtab->dma_q, size);
321 q->dma_q = IVPU_MMU_Q_BASE_RWA;
322 q->dma_q |= q->dma & IVPU_MMU_Q_BASE_ADDR_MASK;
323 q->dma_q |= IVPU_MMU_Q_COUNT_LOG2;
325 ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n",
326 &q->dma, &q->dma_q, IVPU_MMU_CMDQ_SIZE);
340 q->dma_q = IVPU_MMU_Q_BASE_RWA;
341 q->dma_q |= q->dma & IVPU_MMU_Q_BASE_ADDR_MASK;
342 q->dma_q |= IVPU_MMU_Q_COUNT_LOG2;
344 ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n",
345 &q->dma, &q->dma_q, IVPU_MMU_EVTQ_SIZE);
509 REGV_WR64(VPU_37XX_HOST_MMU_STRTAB_BASE, mmu->strtab.dma_q);
512 REGV_WR64(VPU_37XX_HOST_MMU_CMDQ_BASE, mmu->cmdq.dma_q);
533 REGV_WR64(VPU_37XX_HOST_MMU_EVTQ_BASE, mmu->evtq.dma_q);