Lines Matching refs:vdev
110 static void ivpu_hw_read_platform(struct ivpu_device *vdev)
113 vdev->platform = IVPU_PLATFORM_SIMICS;
115 vdev->platform = IVPU_PLATFORM_SILICON;
117 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
118 ivpu_platform_to_str(vdev->platform), vdev->platform);
121 static void ivpu_hw_wa_init(struct ivpu_device *vdev)
123 vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
124 vdev->wa.clear_runtime_mem = false;
126 if (ivpu_hw_gen(vdev) == IVPU_HW_40XX)
127 vdev->wa.disable_clock_relinquish = true;
134 static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
136 if (ivpu_is_fpga(vdev)) {
137 vdev->timeout.boot = 100000;
138 vdev->timeout.jsm = 50000;
139 vdev->timeout.tdr = 2000000;
140 vdev->timeout.reschedule_suspend = 1000;
141 } else if (ivpu_is_simics(vdev)) {
142 vdev->timeout.boot = 50;
143 vdev->timeout.jsm = 500;
144 vdev->timeout.tdr = 10000;
145 vdev->timeout.reschedule_suspend = 10;
147 vdev->timeout.boot = 1000;
148 vdev->timeout.jsm = 500;
149 vdev->timeout.tdr = 2000;
150 vdev->timeout.reschedule_suspend = 10;
154 static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
159 static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio,
165 ret = ivpu_pll_wait_for_cmd_send(vdev);
167 ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret);
190 ret = ivpu_pll_wait_for_cmd_send(vdev);
192 ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret);
197 static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
202 static int ivpu_wait_for_clock_own_resource_ack(struct ivpu_device *vdev)
204 if (ivpu_is_simics(vdev))
210 static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
212 struct ivpu_hw_info *hw = vdev->hw;
228 static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
233 struct ivpu_hw_info *hw = vdev->hw;
237 ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, epp: 0x%x, config: 0x%x, cdyn: 0x%x\n",
240 ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio,
243 ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret);
248 ret = ivpu_pll_wait_for_status_ready(vdev);
250 ivpu_err(vdev, "Timed out waiting for PLL ready status\n");
258 static int ivpu_pll_enable(struct ivpu_device *vdev)
260 return ivpu_pll_drive(vdev, true);
263 static int ivpu_pll_disable(struct ivpu_device *vdev)
265 return ivpu_pll_drive(vdev, false);
268 static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable)
285 static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable)
302 static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
312 static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
322 static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
332 static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
343 static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
354 static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
365 static void ivpu_boot_idle_gen_drive(struct ivpu_device *vdev, bool enable)
377 static int ivpu_boot_host_ss_check(struct ivpu_device *vdev)
381 ret = ivpu_boot_noc_qreqn_check(vdev, 0x0);
383 ivpu_err(vdev, "Failed qreqn check: %d\n", ret);
387 ret = ivpu_boot_noc_qacceptn_check(vdev, 0x0);
389 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
393 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
395 ivpu_err(vdev, "Failed qdeny check %d\n", ret);
400 static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
412 ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
414 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
418 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
420 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
432 static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
434 return ivpu_boot_host_ss_axi_drive(vdev, true);
437 static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
452 ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
454 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
458 ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
460 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
465 static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
467 return ivpu_boot_host_ss_top_noc_drive(vdev, true);
470 static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
485 static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable)
500 static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val)
502 if (ivpu_is_fpga(vdev))
509 static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable)
521 static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
532 static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev)
546 static int ivpu_boot_cpu_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
556 static int ivpu_boot_cpu_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
566 static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
570 ret = ivpu_wait_for_clock_own_resource_ack(vdev);
572 ivpu_err(vdev, "Timed out waiting for clock own resource ACK\n");
576 ivpu_boot_pwr_island_trickle_drive(vdev, true);
577 ivpu_boot_pwr_island_drive(vdev, true);
579 ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1);
581 ivpu_err(vdev, "Timed out waiting for power island status\n");
585 ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0);
587 ivpu_err(vdev, "Failed qrenqn check %d\n", ret);
591 ivpu_boot_host_ss_clk_drive(vdev, true);
592 ivpu_boot_host_ss_rst_drive(vdev, true);
593 ivpu_boot_pwr_island_isolation_drive(vdev, false);
598 static int ivpu_boot_soc_cpu_drive(struct ivpu_device *vdev, bool enable)
610 ret = ivpu_boot_cpu_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
612 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
616 ret = ivpu_boot_cpu_noc_qdeny_check(vdev, 0x0);
618 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
623 static int ivpu_boot_soc_cpu_enable(struct ivpu_device *vdev)
625 return ivpu_boot_soc_cpu_drive(vdev, true);
628 static int ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev)
634 ret = ivpu_boot_soc_cpu_enable(vdev);
636 ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret);
640 val64 = vdev->fw->entry_point;
648 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
649 ivpu_fw_is_cold_boot(vdev) ? "cold boot" : "resume");
654 static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable)
661 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
674 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
696 static int ivpu_hw_40xx_info_init(struct ivpu_device *vdev)
698 struct ivpu_hw_info *hw = vdev->hw;
704 ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);
710 ivpu_err(vdev, "Fuse: Invalid tile disable config (0x%x)\n", tile_disable);
715 ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n",
718 ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", TILE_MAX_NUM);
723 ivpu_pll_init_frequency_ratios(vdev);
725 ivpu_hw_init_range(&vdev->hw->ranges.global, 0x80000000, SZ_512M);
726 ivpu_hw_init_range(&vdev->hw->ranges.user, 0x80000000, SZ_256M);
727 ivpu_hw_init_range(&vdev->hw->ranges.shave, 0x80000000 + SZ_256M, SZ_2G - SZ_256M);
728 ivpu_hw_init_range(&vdev->hw->ranges.dma, 0x200000000, SZ_8G);
730 ivpu_hw_read_platform(vdev);
731 ivpu_hw_wa_init(vdev);
732 ivpu_hw_timeouts_init(vdev);
737 static int ivpu_hw_40xx_reset(struct ivpu_device *vdev)
744 ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");
754 ivpu_err(vdev, "Timed out waiting for RESET completion\n");
759 static int ivpu_hw_40xx_d0i3_enable(struct ivpu_device *vdev)
766 ret = ivpu_boot_d0i3_drive(vdev, true);
768 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
775 static int ivpu_hw_40xx_d0i3_disable(struct ivpu_device *vdev)
782 ret = ivpu_boot_d0i3_drive(vdev, false);
784 ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
789 static void ivpu_hw_40xx_profiling_freq_reg_set(struct ivpu_device *vdev)
793 if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)
801 static void ivpu_hw_40xx_ats_print(struct ivpu_device *vdev)
803 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",
807 static void ivpu_hw_40xx_clock_relinquish_disable(struct ivpu_device *vdev)
815 static int ivpu_hw_40xx_power_up(struct ivpu_device *vdev)
819 ret = ivpu_hw_40xx_reset(vdev);
821 ivpu_err(vdev, "Failed to reset HW: %d\n", ret);
825 ret = ivpu_hw_40xx_d0i3_disable(vdev);
827 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
829 ret = ivpu_pll_enable(vdev);
831 ivpu_err(vdev, "Failed to enable PLL: %d\n", ret);
836 ivpu_hw_40xx_clock_relinquish_disable(vdev);
837 ivpu_hw_40xx_profiling_freq_reg_set(vdev);
838 ivpu_hw_40xx_ats_print(vdev);
840 ret = ivpu_boot_host_ss_check(vdev);
842 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
846 ivpu_boot_idle_gen_drive(vdev, false);
848 ret = ivpu_boot_pwr_domain_enable(vdev);
850 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
854 ret = ivpu_boot_host_ss_axi_enable(vdev);
856 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
860 ret = ivpu_boot_host_ss_top_noc_enable(vdev);
862 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
867 static int ivpu_hw_40xx_boot_fw(struct ivpu_device *vdev)
871 ivpu_boot_no_snoop_enable(vdev);
872 ivpu_boot_tbu_mmu_enable(vdev);
874 ret = ivpu_boot_soc_cpu_boot(vdev);
876 ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret);
881 static bool ivpu_hw_40xx_is_idle(struct ivpu_device *vdev)
893 static int ivpu_hw_40xx_power_down(struct ivpu_device *vdev)
897 if (!ivpu_hw_40xx_is_idle(vdev) && ivpu_hw_40xx_reset(vdev))
898 ivpu_warn(vdev, "Failed to reset the VPU\n");
900 if (ivpu_pll_disable(vdev)) {
901 ivpu_err(vdev, "Failed to disable PLL\n");
905 if (ivpu_hw_40xx_d0i3_enable(vdev)) {
906 ivpu_err(vdev, "Failed to enter D0I3\n");
913 static void ivpu_hw_40xx_wdt_disable(struct ivpu_device *vdev)
929 static u32 ivpu_hw_40xx_reg_pll_freq_get(struct ivpu_device *vdev)
939 static u32 ivpu_hw_40xx_reg_telemetry_offset_get(struct ivpu_device *vdev)
944 static u32 ivpu_hw_40xx_reg_telemetry_size_get(struct ivpu_device *vdev)
949 static u32 ivpu_hw_40xx_reg_telemetry_enable_get(struct ivpu_device *vdev)
954 static void ivpu_hw_40xx_reg_db_set(struct ivpu_device *vdev, u32 db_id)
962 static u32 ivpu_hw_40xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev)
967 static u32 ivpu_hw_40xx_reg_ipc_rx_count_get(struct ivpu_device *vdev)
974 static void ivpu_hw_40xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
979 static void ivpu_hw_40xx_irq_clear(struct ivpu_device *vdev)
984 static void ivpu_hw_40xx_irq_enable(struct ivpu_device *vdev)
992 static void ivpu_hw_40xx_irq_disable(struct ivpu_device *vdev)
1000 static void ivpu_hw_40xx_irq_wdt_nce_handler(struct ivpu_device *vdev)
1003 ivpu_pm_schedule_recovery(vdev);
1006 static void ivpu_hw_40xx_irq_wdt_mss_handler(struct ivpu_device *vdev)
1008 ivpu_hw_wdt_disable(vdev);
1009 ivpu_pm_schedule_recovery(vdev);
1012 static void ivpu_hw_40xx_irq_noc_firewall_handler(struct ivpu_device *vdev)
1014 ivpu_pm_schedule_recovery(vdev);
1018 static irqreturn_t ivpu_hw_40xx_irqv_handler(struct ivpu_device *vdev, int irq)
1029 ivpu_mmu_irq_evtq_handler(vdev);
1032 ret |= ivpu_ipc_irq_handler(vdev);
1035 ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
1038 ivpu_mmu_irq_gerr_handler(vdev);
1041 ivpu_hw_40xx_irq_wdt_mss_handler(vdev);
1044 ivpu_hw_40xx_irq_wdt_nce_handler(vdev);
1047 ivpu_hw_40xx_irq_noc_firewall_handler(vdev);
1053 static irqreturn_t ivpu_hw_40xx_irqb_handler(struct ivpu_device *vdev, int irq)
1062 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE");
1065 ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
1073 ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
1079 ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
1085 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",
1093 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",
1101 ivpu_err(vdev, "Survivability error detected\n");
1109 ivpu_pm_schedule_recovery(vdev);
1116 struct ivpu_device *vdev = ptr;
1121 ret |= ivpu_hw_40xx_irqv_handler(vdev, irq);
1122 ret |= ivpu_hw_40xx_irqb_handler(vdev, irq);
1133 static void ivpu_hw_40xx_diagnose_failure(struct ivpu_device *vdev)
1138 if (ivpu_hw_40xx_reg_ipc_rx_count_get(vdev))
1139 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
1142 ivpu_err(vdev, "WDT MSS timeout detected\n");
1145 ivpu_err(vdev, "WDT NCE timeout detected\n");
1148 ivpu_err(vdev, "NOC Firewall irq detected\n");
1151 ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
1157 ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));
1160 ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));
1163 ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",
1168 ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",
1173 ivpu_err(vdev, "Survivability error detected\n");