Lines Matching refs:vdev
87 static void ivpu_hw_read_platform(struct ivpu_device *vdev)
93 vdev->platform = platform;
95 vdev->platform = IVPU_PLATFORM_SILICON;
97 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
98 ivpu_platform_to_str(vdev->platform), vdev->platform);
101 static void ivpu_hw_wa_init(struct ivpu_device *vdev)
103 vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
104 vdev->wa.clear_runtime_mem = false;
105 vdev->wa.d3hot_after_power_off = true;
110 vdev->wa.interrupt_clear_with_0 = true;
120 static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
122 if (ivpu_is_simics(vdev) || ivpu_is_fpga(vdev)) {
123 vdev->timeout.boot = 100000;
124 vdev->timeout.jsm = 50000;
125 vdev->timeout.tdr = 2000000;
126 vdev->timeout.reschedule_suspend = 1000;
128 vdev->timeout.boot = 1000;
129 vdev->timeout.jsm = 500;
130 vdev->timeout.tdr = 2000;
131 vdev->timeout.reschedule_suspend = 10;
135 static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
141 static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio,
147 ret = ivpu_pll_wait_for_cmd_send(vdev);
149 ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret);
171 ret = ivpu_pll_wait_for_cmd_send(vdev);
173 ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret);
178 static int ivpu_pll_wait_for_lock(struct ivpu_device *vdev, bool enable)
188 static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev)
196 static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev)
198 struct ivpu_hw_info *hw = vdev->hw;
214 static int ivpu_hw_37xx_wait_for_vpuip_bar(struct ivpu_device *vdev)
219 static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)
221 struct ivpu_hw_info *hw = vdev->hw;
227 ivpu_dbg(vdev, PM, "Skipping PLL request on %s\n",
228 ivpu_platform_to_str(vdev->platform));
240 ivpu_dbg(vdev, PM, "PLL workpoint request: config 0x%04x pll ratio 0x%x\n",
243 ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio, target_ratio, config);
245 ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret);
249 ret = ivpu_pll_wait_for_lock(vdev, enable);
251 ivpu_err(vdev, "Timed out waiting for PLL lock\n");
256 ret = ivpu_pll_wait_for_status_ready(vdev);
258 ivpu_err(vdev, "Timed out waiting for PLL ready status\n");
262 ret = ivpu_hw_37xx_wait_for_vpuip_bar(vdev);
264 ivpu_err(vdev, "Timed out waiting for VPUIP bar\n");
272 static int ivpu_pll_enable(struct ivpu_device *vdev)
274 return ivpu_pll_drive(vdev, true);
277 static int ivpu_pll_disable(struct ivpu_device *vdev)
279 return ivpu_pll_drive(vdev, false);
282 static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev)
293 static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable)
310 static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable)
327 static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val)
337 static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
347 static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
357 static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val)
368 static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val)
379 static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val)
390 static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev)
392 ivpu_boot_host_ss_rst_clr_assert(vdev);
394 return ivpu_boot_noc_qreqn_check(vdev, 0x0);
397 static void ivpu_boot_vpu_idle_gen_disable(struct ivpu_device *vdev)
402 static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable)
414 ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
416 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
420 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0);
422 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
427 static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev)
429 return ivpu_boot_host_ss_axi_drive(vdev, true);
432 static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable)
447 ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0);
449 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
453 ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0);
455 ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
460 static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev)
462 return ivpu_boot_host_ss_top_noc_drive(vdev, true);
465 static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable)
477 static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable)
489 static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val)
492 if (ivpu_is_fpga(vdev))
499 static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable)
511 static void ivpu_boot_dpu_active_drive(struct ivpu_device *vdev, bool enable)
523 static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev)
527 ivpu_boot_pwr_island_trickle_drive(vdev, true);
528 ivpu_boot_pwr_island_drive(vdev, true);
530 ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1);
532 ivpu_err(vdev, "Timed out waiting for power island status\n");
536 ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0);
538 ivpu_err(vdev, "Failed qrenqn check %d\n", ret);
542 ivpu_boot_host_ss_clk_drive(vdev, true);
543 ivpu_boot_pwr_island_isolation_drive(vdev, false);
544 ivpu_boot_host_ss_rst_drive(vdev, true);
545 ivpu_boot_dpu_active_drive(vdev, true);
550 static int ivpu_boot_pwr_domain_disable(struct ivpu_device *vdev)
552 ivpu_boot_dpu_active_drive(vdev, false);
553 ivpu_boot_pwr_island_isolation_drive(vdev, true);
554 ivpu_boot_pwr_island_trickle_drive(vdev, false);
555 ivpu_boot_pwr_island_drive(vdev, false);
557 return ivpu_boot_wait_for_pwr_island_status(vdev, 0x0);
560 static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev)
571 static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev)
583 static void ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev)
599 val = vdev->fw->entry_point >> 9;
605 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n",
606 vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume");
609 static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable)
616 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
629 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
634 static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev)
636 struct ivpu_hw_info *hw = vdev->hw;
642 ivpu_pll_init_frequency_ratios(vdev);
649 ivpu_hw_read_platform(vdev);
650 ivpu_hw_wa_init(vdev);
651 ivpu_hw_timeouts_init(vdev);
656 static int ivpu_hw_37xx_reset(struct ivpu_device *vdev)
660 if (ivpu_boot_pwr_domain_disable(vdev)) {
661 ivpu_err(vdev, "Failed to disable power domain\n");
665 if (ivpu_pll_disable(vdev)) {
666 ivpu_err(vdev, "Failed to disable PLL\n");
673 static int ivpu_hw_37xx_d0i3_enable(struct ivpu_device *vdev)
677 ret = ivpu_boot_d0i3_drive(vdev, true);
679 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
686 static int ivpu_hw_37xx_d0i3_disable(struct ivpu_device *vdev)
690 ret = ivpu_boot_d0i3_drive(vdev, false);
692 ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
697 static int ivpu_hw_37xx_power_up(struct ivpu_device *vdev)
701 ret = ivpu_hw_37xx_d0i3_disable(vdev);
703 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret);
705 ret = ivpu_pll_enable(vdev);
707 ivpu_err(vdev, "Failed to enable PLL: %d\n", ret);
711 ret = ivpu_boot_host_ss_configure(vdev);
713 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
722 ivpu_boot_vpu_idle_gen_disable(vdev);
724 ret = ivpu_boot_pwr_domain_enable(vdev);
726 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
730 ret = ivpu_boot_host_ss_axi_enable(vdev);
732 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
736 ret = ivpu_boot_host_ss_top_noc_enable(vdev);
738 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
743 static int ivpu_hw_37xx_boot_fw(struct ivpu_device *vdev)
745 ivpu_boot_no_snoop_enable(vdev);
746 ivpu_boot_tbu_mmu_enable(vdev);
747 ivpu_boot_soc_cpu_boot(vdev);
752 static bool ivpu_hw_37xx_is_idle(struct ivpu_device *vdev)
764 static int ivpu_hw_37xx_power_down(struct ivpu_device *vdev)
768 if (!ivpu_hw_37xx_is_idle(vdev))
769 ivpu_warn(vdev, "VPU not idle during power down\n");
771 if (ivpu_hw_37xx_reset(vdev)) {
772 ivpu_err(vdev, "Failed to reset VPU\n");
776 if (ivpu_hw_37xx_d0i3_enable(vdev)) {
777 ivpu_err(vdev, "Failed to enter D0I3\n");
784 static void ivpu_hw_37xx_wdt_disable(struct ivpu_device *vdev)
816 static u32 ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device *vdev)
823 if (!ivpu_is_silicon(vdev))
826 return ivpu_hw_37xx_pll_to_freq(pll_curr_ratio, vdev->hw->config);
829 static u32 ivpu_hw_37xx_reg_telemetry_offset_get(struct ivpu_device *vdev)
834 static u32 ivpu_hw_37xx_reg_telemetry_size_get(struct ivpu_device *vdev)
839 static u32 ivpu_hw_37xx_reg_telemetry_enable_get(struct ivpu_device *vdev)
844 static void ivpu_hw_37xx_reg_db_set(struct ivpu_device *vdev, u32 db_id)
852 static u32 ivpu_hw_37xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev)
857 static u32 ivpu_hw_37xx_reg_ipc_rx_count_get(struct ivpu_device *vdev)
864 static void ivpu_hw_37xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
869 static void ivpu_hw_37xx_irq_clear(struct ivpu_device *vdev)
874 static void ivpu_hw_37xx_irq_enable(struct ivpu_device *vdev)
882 static void ivpu_hw_37xx_irq_disable(struct ivpu_device *vdev)
890 static void ivpu_hw_37xx_irq_wdt_nce_handler(struct ivpu_device *vdev)
892 ivpu_err_ratelimited(vdev, "WDT NCE irq\n");
894 ivpu_pm_schedule_recovery(vdev);
897 static void ivpu_hw_37xx_irq_wdt_mss_handler(struct ivpu_device *vdev)
899 ivpu_err_ratelimited(vdev, "WDT MSS irq\n");
901 ivpu_hw_wdt_disable(vdev);
902 ivpu_pm_schedule_recovery(vdev);
905 static void ivpu_hw_37xx_irq_noc_firewall_handler(struct ivpu_device *vdev)
907 ivpu_err_ratelimited(vdev, "NOC Firewall irq\n");
909 ivpu_pm_schedule_recovery(vdev);
913 static u32 ivpu_hw_37xx_irqv_handler(struct ivpu_device *vdev, int irq)
920 ivpu_mmu_irq_evtq_handler(vdev);
923 ivpu_ipc_irq_handler(vdev);
926 ivpu_dbg(vdev, IRQ, "MMU sync complete\n");
929 ivpu_mmu_irq_gerr_handler(vdev);
932 ivpu_hw_37xx_irq_wdt_mss_handler(vdev);
935 ivpu_hw_37xx_irq_wdt_nce_handler(vdev);
938 ivpu_hw_37xx_irq_noc_firewall_handler(vdev);
944 static u32 ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq)
953 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x",
957 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0));
965 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
984 ivpu_pm_schedule_recovery(vdev);
991 struct ivpu_device *vdev = ptr;
996 ret_irqv = ivpu_hw_37xx_irqv_handler(vdev, irq);
997 ret_irqb = ivpu_hw_37xx_irqb_handler(vdev, irq);
1005 static void ivpu_hw_37xx_diagnose_failure(struct ivpu_device *vdev)
1010 if (ivpu_hw_37xx_reg_ipc_rx_count_get(vdev))
1011 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
1014 ivpu_err(vdev, "WDT MSS timeout detected\n");
1017 ivpu_err(vdev, "WDT NCE timeout detected\n");
1020 ivpu_err(vdev, "NOC Firewall irq detected\n");
1023 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0));
1028 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",