Lines Matching defs:val
615 u32 fw_boot_status, val;
688 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
689 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
1446 u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1459 val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1460 if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1464 WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1483 val,
1484 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1505 val = RREG32(tpc_slm_offset);
4177 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4179 WREG32(mmCPU_EQ_CI, val);
4224 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4231 writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4460 u32 val;
4465 val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4466 if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4467 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4766 u64 val, bool is_dram)
4795 lin_dma_pkt->src_addr = cpu_to_le64(val);
4842 u64 val = 0x7777777777777777ull;
4847 rc = goya_memset_device_memory(hdev, addr, size, val, false);
4890 u64 val = 0x9999999999999999ull;
4895 return goya_memset_device_memory(hdev, addr, size, val, true);
5423 static int goya_scrub_device_dram(struct hl_device *hdev, u64 val)