Lines Matching defs:hdev
355 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
356 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
357 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
358 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
360 int goya_set_fixed_properties(struct hl_device *hdev)
362 struct asic_fixed_properties *prop = &hdev->asic_prop;
411 if (hdev->pldm)
504 * @hdev: pointer to hl_device structure
510 static int goya_pci_bars_map(struct hl_device *hdev)
516 rc = hl_pci_bars_map(hdev, name, is_wc);
520 hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
526 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
528 struct goya_device *goya = hdev->asic_specific;
540 rc = hl_pci_set_inbound_region(hdev, 1, &pci_region);
555 * @hdev: pointer to hl_device structure
560 static int goya_init_iatu(struct hl_device *hdev)
566 if (hdev->asic_prop.iatu_done_by_fw)
573 rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
581 rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
588 rc = hl_pci_set_outbound_region(hdev, &outbound_region);
594 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
602 * @hdev: pointer to hl_device structure
610 static int goya_early_init(struct hl_device *hdev)
612 struct asic_fixed_properties *prop = &hdev->asic_prop;
613 struct pci_dev *pdev = hdev->pdev;
618 rc = goya_set_fixed_properties(hdev);
620 dev_err(hdev->dev, "Failed to get fixed properties\n");
628 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
637 dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
644 hdev->dram_pci_bar_start = pci_resource_start(pdev, DDR_BAR_ID);
647 if (hdev->asic_prop.fw_security_enabled) {
648 hdev->asic_prop.iatu_done_by_fw = true;
652 rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
660 hdev->asic_prop.iatu_done_by_fw = true;
663 rc = hl_pci_init(hdev);
670 rc = hl_fw_read_preboot_status(hdev);
672 if (hdev->reset_on_preboot_fail)
674 hdev->asic_funcs->hw_fini(hdev, true, false);
678 if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
679 dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n");
680 rc = hdev->asic_funcs->hw_fini(hdev, true, false);
682 dev_err(hdev->dev, "failed to reset HW in dirty state (%d)\n", rc);
687 if (!hdev->pldm) {
690 dev_warn(hdev->dev,
697 hl_pci_fini(hdev);
699 kfree(hdev->asic_prop.hw_queues_props);
706 * @hdev: pointer to hl_device structure
711 static int goya_early_fini(struct hl_device *hdev)
713 kfree(hdev->asic_prop.hw_queues_props);
714 hl_pci_fini(hdev);
719 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
726 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
728 struct goya_device *goya = hdev->asic_specific;
744 * @hdev: pointer to hl_device structure
747 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
749 struct asic_fixed_properties *prop = &hdev->asic_prop;
754 if (hdev->asic_prop.fw_security_enabled) {
755 struct goya_device *goya = hdev->asic_specific;
760 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
789 dev_warn(hdev->dev,
806 * @hdev: pointer to habanalabs device structure
816 int goya_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq)
818 struct goya_device *goya = hdev->asic_specific;
824 dev_dbg(hdev->dev, "Changing device frequency to %s\n",
827 goya_set_pll_profile(hdev, freq);
839 struct hl_device *hdev = goya_work->hdev;
841 mutex_lock(&hdev->fpriv_list_lock);
843 if (!hdev->is_compute_ctx_active)
844 goya_set_frequency(hdev, PLL_LOW);
846 mutex_unlock(&hdev->fpriv_list_lock);
852 int goya_late_init(struct hl_device *hdev)
854 struct asic_fixed_properties *prop = &hdev->asic_prop;
855 struct goya_device *goya = hdev->asic_specific;
858 goya_fetch_psoc_frequency(hdev);
860 rc = goya_mmu_clear_pgt_range(hdev);
862 dev_err(hdev->dev,
867 rc = goya_mmu_set_dram_default_page(hdev);
869 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc);
873 rc = goya_mmu_add_mappings_for_device_cpu(hdev);
877 rc = goya_init_cpu_queues(hdev);
881 rc = goya_test_cpu_queue(hdev);
885 rc = goya_cpucp_info_get(hdev);
887 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc);
897 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS, 0x0);
899 dev_err(hdev->dev,
909 goya_set_pll_profile(hdev, PLL_LOW);
920 * @hdev: pointer to hl_device structure
924 void goya_late_fini(struct hl_device *hdev)
926 struct goya_device *goya = hdev->asic_specific;
930 hl_hwmon_release_resources(hdev);
933 static void goya_set_pci_memory_regions(struct hl_device *hdev)
935 struct asic_fixed_properties *prop = &hdev->asic_prop;
939 region = &hdev->pci_mem_region[PCI_REGION_CFG];
948 region = &hdev->pci_mem_region[PCI_REGION_SRAM];
957 region = &hdev->pci_mem_region[PCI_REGION_DRAM];
959 region->region_size = hdev->asic_prop.dram_size;
969 * @hdev: pointer to hl_device structure
972 static int goya_sw_init(struct hl_device *hdev)
989 hdev->asic_specific = goya;
992 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
993 &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
994 if (!hdev->dma_pool) {
995 dev_err(hdev->dev, "failed to create DMA pool\n");
1000 hdev->cpu_accessible_dma_mem = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE,
1001 &hdev->cpu_accessible_dma_address,
1004 if (!hdev->cpu_accessible_dma_mem) {
1009 dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n",
1010 &hdev->cpu_accessible_dma_address);
1012 hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
1013 if (!hdev->cpu_accessible_dma_pool) {
1014 dev_err(hdev->dev,
1020 rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
1021 (uintptr_t) hdev->cpu_accessible_dma_mem,
1024 dev_err(hdev->dev,
1031 hdev->supports_coresight = true;
1032 hdev->asic_prop.supports_compute_reset = true;
1033 hdev->asic_prop.allow_inference_soft_reset = true;
1034 hdev->supports_wait_for_multi_cs = false;
1035 hdev->supports_ctx_switch = true;
1037 hdev->asic_funcs->set_pci_memory_regions(hdev);
1045 goya->goya_work->hdev = hdev;
1051 gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1053 hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
1054 hdev->cpu_accessible_dma_address);
1056 dma_pool_destroy(hdev->dma_pool);
1066 * @hdev: pointer to hl_device structure
1069 static int goya_sw_fini(struct hl_device *hdev)
1071 struct goya_device *goya = hdev->asic_specific;
1073 gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1075 hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
1076 hdev->cpu_accessible_dma_address);
1078 dma_pool_destroy(hdev->dma_pool);
1086 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
1089 struct goya_device *goya = hdev->asic_specific;
1131 if (hdev->stop_on_err)
1138 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
1167 * @hdev: pointer to hl_device structure
1172 void goya_init_dma_qmans(struct hl_device *hdev)
1174 struct goya_device *goya = hdev->asic_specific;
1181 q = &hdev->kernel_queues[0];
1185 goya_init_dma_qman(hdev, i, q->bus_address);
1186 goya_init_dma_ch(hdev, i);
1195 * @hdev: pointer to hl_device structure
1198 static void goya_disable_external_queues(struct hl_device *hdev)
1200 struct goya_device *goya = hdev->asic_specific;
1212 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1225 hdev,
1238 hdev,
1246 dev_err(hdev->dev,
1257 * @hdev: pointer to hl_device structure
1262 static int goya_stop_external_queues(struct hl_device *hdev)
1266 struct goya_device *goya = hdev->asic_specific;
1271 rc = goya_stop_queue(hdev,
1277 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1281 rc = goya_stop_queue(hdev,
1287 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1291 rc = goya_stop_queue(hdev,
1297 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1301 rc = goya_stop_queue(hdev,
1307 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1311 rc = goya_stop_queue(hdev,
1317 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1327 * @hdev: pointer to hl_device structure
1332 int goya_init_cpu_queues(struct hl_device *hdev)
1334 struct goya_device *goya = hdev->asic_specific;
1335 struct asic_fixed_properties *prop = &hdev->asic_prop;
1338 struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1341 if (!hdev->cpu_queues_enable)
1347 eq = &hdev->event_queue;
1375 hdev,
1383 dev_err(hdev->dev,
1399 static void goya_set_pll_refclk(struct hl_device *hdev)
1437 static void goya_disable_clk_rlx(struct hl_device *hdev)
1443 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1461 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1481 hdev,
1489 dev_err(hdev->dev,
1508 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1510 struct goya_device *goya = hdev->asic_specific;
1513 if (hdev->pldm)
1522 _goya_tpc_mbist_workaround(hdev, i);
1530 * @hdev: pointer to hl_device structure
1535 static void goya_init_golden_registers(struct hl_device *hdev)
1537 struct goya_device *goya = hdev->asic_specific;
1830 static void goya_init_mme_qman(struct hl_device *hdev)
1847 qman_base_addr = hdev->asic_prop.sram_base_address +
1880 static void goya_init_mme_cmdq(struct hl_device *hdev)
1916 void goya_init_mme_qmans(struct hl_device *hdev)
1918 struct goya_device *goya = hdev->asic_specific;
1930 goya_init_mme_qman(hdev);
1931 goya_init_mme_cmdq(hdev);
1936 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1954 qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1986 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
2023 void goya_init_tpc_qmans(struct hl_device *hdev)
2025 struct goya_device *goya = hdev->asic_specific;
2044 goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
2045 goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
2046 goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
2047 goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
2048 goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
2049 goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
2050 goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
2051 goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
2054 goya_init_tpc_cmdq(hdev, i);
2062 * @hdev: pointer to hl_device structure
2065 static void goya_disable_internal_queues(struct hl_device *hdev)
2067 struct goya_device *goya = hdev->asic_specific;
2107 * @hdev: pointer to hl_device structure
2112 static int goya_stop_internal_queues(struct hl_device *hdev)
2114 struct goya_device *goya = hdev->asic_specific;
2126 rc = goya_stop_queue(hdev,
2132 dev_err(hdev->dev, "failed to stop MME QMAN\n");
2136 rc = goya_stop_queue(hdev,
2142 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
2150 rc = goya_stop_queue(hdev,
2156 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
2160 rc = goya_stop_queue(hdev,
2166 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
2170 rc = goya_stop_queue(hdev,
2176 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2180 rc = goya_stop_queue(hdev,
2186 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2190 rc = goya_stop_queue(hdev,
2196 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2200 rc = goya_stop_queue(hdev,
2206 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2210 rc = goya_stop_queue(hdev,
2216 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2220 rc = goya_stop_queue(hdev,
2226 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2230 rc = goya_stop_queue(hdev,
2236 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2240 rc = goya_stop_queue(hdev,
2246 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2250 rc = goya_stop_queue(hdev,
2256 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2260 rc = goya_stop_queue(hdev,
2266 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2270 rc = goya_stop_queue(hdev,
2276 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2280 rc = goya_stop_queue(hdev,
2286 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2290 rc = goya_stop_queue(hdev,
2296 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2300 rc = goya_stop_queue(hdev,
2306 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2313 static void goya_dma_stall(struct hl_device *hdev)
2315 struct goya_device *goya = hdev->asic_specific;
2327 static void goya_tpc_stall(struct hl_device *hdev)
2329 struct goya_device *goya = hdev->asic_specific;
2344 static void goya_mme_stall(struct hl_device *hdev)
2346 struct goya_device *goya = hdev->asic_specific;
2354 static int goya_enable_msix(struct hl_device *hdev)
2356 struct goya_device *goya = hdev->asic_specific;
2357 int cq_cnt = hdev->asic_prop.completion_queues_count;
2363 rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2366 dev_err(hdev->dev,
2373 irq = pci_irq_vector(hdev->pdev, i);
2375 &hdev->completion_queue[i]);
2377 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2382 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2386 &hdev->event_queue);
2388 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2397 free_irq(pci_irq_vector(hdev->pdev, i),
2398 &hdev->completion_queue[i]);
2400 pci_free_irq_vectors(hdev->pdev);
2404 static void goya_sync_irqs(struct hl_device *hdev)
2406 struct goya_device *goya = hdev->asic_specific;
2413 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2414 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2416 synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2419 static void goya_disable_msix(struct hl_device *hdev)
2421 struct goya_device *goya = hdev->asic_specific;
2427 goya_sync_irqs(hdev);
2429 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2430 free_irq(irq, &hdev->event_queue);
2432 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2433 irq = pci_irq_vector(hdev->pdev, i);
2434 free_irq(irq, &hdev->completion_queue[i]);
2437 pci_free_irq_vectors(hdev->pdev);
2442 static void goya_enable_timestamp(struct hl_device *hdev)
2455 static void goya_disable_timestamp(struct hl_device *hdev)
2461 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2465 if (hdev->pldm)
2470 goya_stop_external_queues(hdev);
2471 goya_stop_internal_queues(hdev);
2475 goya_dma_stall(hdev);
2476 goya_tpc_stall(hdev);
2477 goya_mme_stall(hdev);
2481 goya_disable_external_queues(hdev);
2482 goya_disable_internal_queues(hdev);
2484 goya_disable_timestamp(hdev);
2487 goya_disable_msix(hdev);
2488 goya_mmu_remove_device_cpu_mappings(hdev);
2490 goya_sync_irqs(hdev);
2496 * @hdev: Pointer to hl_device structure.
2502 static int goya_load_firmware_to_device(struct hl_device *hdev)
2506 dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2508 return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0);
2513 * @hdev: Pointer to hl_device structure.
2519 static int goya_load_boot_fit_to_device(struct hl_device *hdev)
2523 dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
2525 return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
2528 static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
2533 dynamic_loader = &hdev->fw_loader.dynamic_loader;
2551 static void goya_init_static_firmware_loader(struct hl_device *hdev)
2555 static_loader = &hdev->fw_loader.static_loader;
2571 static void goya_init_firmware_preload_params(struct hl_device *hdev)
2573 struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load;
2583 static void goya_init_firmware_loader(struct hl_device *hdev)
2585 struct asic_fixed_properties *prop = &hdev->asic_prop;
2586 struct fw_load_mgr *fw_loader = &hdev->fw_loader;
2599 goya_init_dynamic_firmware_loader(hdev);
2601 goya_init_static_firmware_loader(hdev);
2604 static int goya_init_cpu(struct hl_device *hdev)
2606 struct goya_device *goya = hdev->asic_specific;
2609 if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
2619 if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
2620 dev_err(hdev->dev,
2625 rc = hl_fw_init_cpu(hdev);
2635 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2641 if (hdev->pldm)
2651 hdev,
2659 dev_err(hdev->dev,
2667 int goya_mmu_init(struct hl_device *hdev)
2669 struct asic_fixed_properties *prop = &hdev->asic_prop;
2670 struct goya_device *goya = hdev->asic_specific;
2677 hdev->dram_default_page_mapping = true;
2683 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2685 dev_err(hdev->dev,
2702 hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR | MMU_OP_PHYS_PACK);
2716 * @hdev: pointer to hl_device structure
2721 static int goya_hw_init(struct hl_device *hdev)
2723 struct asic_fixed_properties *prop = &hdev->asic_prop;
2737 rc = goya_init_cpu(hdev);
2739 dev_err(hdev->dev, "failed to initialize CPU\n");
2743 goya_tpc_mbist_workaround(hdev);
2745 goya_init_golden_registers(hdev);
2751 if (goya_set_ddr_bar_base(hdev, (MMU_PAGE_TABLES_ADDR &
2753 dev_err(hdev->dev,
2758 rc = goya_mmu_init(hdev);
2762 goya_init_security(hdev);
2764 goya_init_dma_qmans(hdev);
2766 goya_init_mme_qmans(hdev);
2768 goya_init_tpc_qmans(hdev);
2770 goya_enable_timestamp(hdev);
2773 rc = goya_enable_msix(hdev);
2783 goya_disable_internal_queues(hdev);
2784 goya_disable_external_queues(hdev);
2789 static int goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2791 struct goya_device *goya = hdev->asic_specific;
2794 if (hdev->pldm) {
2812 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2813 goya_disable_clk_rlx(hdev);
2814 goya_set_pll_refclk(hdev);
2817 dev_dbg(hdev->dev,
2822 dev_dbg(hdev->dev,
2836 dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", status);
2867 int goya_suspend(struct hl_device *hdev)
2871 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0);
2873 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2878 int goya_resume(struct hl_device *hdev)
2880 return goya_init_iatu(hdev);
2883 static int goya_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2891 rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
2894 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
2899 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2966 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n",
2984 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2990 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2993 void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
3003 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
3009 dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
3012 int goya_scrub_device_mem(struct hl_device *hdev)
3017 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
3023 *dma_handle = hdev->asic_prop.sram_base_address;
3025 base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
3065 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
3075 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
3084 if (hdev->pldm)
3089 if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
3090 dev_err_ratelimited(hdev->dev,
3095 fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
3097 dev_err(hdev->dev,
3102 goya_qman0_set_security(hdev, true);
3116 rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
3119 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
3123 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
3127 hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
3130 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
3135 hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
3137 goya_qman0_set_security(hdev, false);
3142 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
3145 struct goya_device *goya = hdev->asic_specific;
3156 return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
3160 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
3171 fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
3173 dev_err(hdev->dev,
3181 fence_pkt = hl_asic_dma_pool_zalloc(hdev, sizeof(struct packet_msg_prot), GFP_KERNEL,
3184 dev_err(hdev->dev,
3198 rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3202 dev_err(hdev->dev,
3208 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
3211 hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3214 dev_err(hdev->dev,
3221 hl_asic_dma_pool_free(hdev, (void *) fence_pkt, pkt_dma_addr);
3223 hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
3227 int goya_test_cpu_queue(struct hl_device *hdev)
3229 struct goya_device *goya = hdev->asic_specific;
3238 return hl_fw_test_cpu_queue(hdev);
3241 int goya_test_queues(struct hl_device *hdev)
3246 rc = goya_test_queue(hdev, i);
3254 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3262 kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3271 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3277 dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
3280 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3285 vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3286 *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address +
3292 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3295 hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3298 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3338 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3346 if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3354 rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3361 rc = hdev->asic_funcs->asic_dma_map_sgtable(hdev, userptr->sgt, dir);
3363 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3372 goya_get_dma_desc_list_size(hdev, userptr->sgt);
3378 hl_unpin_host_memory(hdev, userptr);
3384 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3407 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3417 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3425 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3434 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3440 dev_err(hdev->dev, "DMA direction %d is unsupported/undefined\n", user_dir);
3447 hdev->asic_prop.sram_user_base_address,
3448 hdev->asic_prop.sram_end_address)) {
3450 dev_err(hdev->dev,
3459 hdev->asic_prop.dram_user_base_address,
3460 hdev->asic_prop.dram_end_address)) {
3462 dev_err(hdev->dev,
3475 dev_err(hdev->dev,
3480 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3487 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3500 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3504 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3511 hdev->asic_prop.sram_user_base_address,
3512 hdev->asic_prop.sram_end_address)) {
3513 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3520 hdev->asic_prop.dram_user_base_address,
3521 hdev->asic_prop.dram_end_address)) {
3522 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3532 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3540 dev_dbg(hdev->dev, "DMA packet details:\n");
3541 dev_dbg(hdev->dev, "source == 0x%llx\n",
3543 dev_dbg(hdev->dev, "destination == 0x%llx\n",
3545 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3556 dev_err(hdev->dev,
3562 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3564 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3569 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3573 dev_dbg(hdev->dev, "DMA packet details:\n");
3574 dev_dbg(hdev->dev, "source == 0x%llx\n",
3576 dev_dbg(hdev->dev, "destination == 0x%llx\n",
3578 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3588 hdev->asic_prop.pmmu.start_addr,
3589 hdev->asic_prop.pmmu.end_addr)) {
3590 dev_err(hdev->dev,
3596 dev_err(hdev->dev,
3606 static int goya_validate_wreg32(struct hl_device *hdev,
3610 struct goya_device *goya = hdev->asic_specific;
3617 dev_dbg(hdev->dev, "WREG32 packet details:\n");
3618 dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3619 dev_dbg(hdev->dev, "value == 0x%x\n",
3623 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3642 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3650 static int goya_validate_cb(struct hl_device *hdev,
3672 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3680 dev_err(hdev->dev,
3693 rc = goya_validate_wreg32(hdev,
3699 dev_err(hdev->dev,
3705 dev_err(hdev->dev,
3711 dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3716 dev_err(hdev->dev, "User not allowed to use STOP\n");
3722 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3725 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3737 dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3757 static int goya_patch_dma_packet(struct hl_device *hdev,
3804 (hl_userptr_is_pinned(hdev, addr,
3807 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3873 dev_err(hdev->dev,
3887 static int goya_patch_cb(struct hl_device *hdev,
3911 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3919 dev_err(hdev->dev,
3927 rc = goya_patch_dma_packet(hdev, parser,
3937 rc = goya_validate_wreg32(hdev, parser,
3942 dev_err(hdev->dev,
3948 dev_err(hdev->dev,
3954 dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3959 dev_err(hdev->dev, "User not allowed to use STOP\n");
3972 dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3985 static int goya_parse_cb_mmu(struct hl_device *hdev,
4001 rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
4006 dev_err(hdev->dev,
4012 parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
4015 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
4033 rc = goya_validate_cb(hdev, parser, true);
4042 dev_err(hdev->dev, "user CB size mismatch\n");
4055 hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
4060 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
4066 rc = goya_validate_cb(hdev, parser, false);
4071 rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
4075 dev_err(hdev->dev,
4080 parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
4083 dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
4088 rc = goya_patch_cb(hdev, parser);
4100 hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
4104 hl_userptr_delete_list(hdev, parser->job_userptr_list);
4108 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
4111 struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
4112 struct goya_device *goya = hdev->asic_specific;
4132 dev_err(hdev->dev,
4139 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
4141 struct goya_device *goya = hdev->asic_specific;
4144 return goya_parse_cb_no_ext_queue(hdev, parser);
4147 return goya_parse_cb_mmu(hdev, parser);
4149 return goya_parse_cb_no_mmu(hdev, parser);
4152 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
4177 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4182 void goya_restore_phase_topology(struct hl_device *hdev)
4187 static void goya_clear_sm_regs(struct hl_device *hdev)
4207 static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, void *blob_addr)
4209 dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");
4213 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4215 struct goya_device *goya = hdev->asic_specific;
4217 if (hdev->reset_info.hard_reset_pending)
4220 return readq(hdev->pcie_bar[DDR_BAR_ID] +
4224 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4226 struct goya_device *goya = hdev->asic_specific;
4228 if (hdev->reset_info.hard_reset_pending)
4231 writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4433 static void goya_print_razwi_info(struct hl_device *hdev)
4436 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n");
4441 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n");
4446 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n");
4451 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n");
4456 static void goya_print_mmu_error_info(struct hl_device *hdev)
4458 struct goya_device *goya = hdev->asic_specific;
4471 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n",
4478 static void goya_print_out_of_sync_info(struct hl_device *hdev,
4481 struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
4483 dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d\n",
4487 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
4493 dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4497 goya_print_razwi_info(hdev);
4498 goya_print_mmu_error_info(hdev);
4502 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4520 dev_err(hdev->dev, "too many elements in IRQ array\n");
4542 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4546 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4553 static int goya_compute_reset_late_init(struct hl_device *hdev)
4559 return goya_unmask_irq_arr(hdev, goya_all_events,
4563 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4575 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4579 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4584 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
4588 mutex_lock(&hdev->clk_throttling.lock);
4592 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER;
4593 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER;
4594 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get();
4595 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time;
4596 dev_info_ratelimited(hdev->dev,
4601 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER;
4602 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get();
4603 dev_info_ratelimited(hdev->dev,
4608 hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL;
4609 hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL;
4610 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get();
4611 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time;
4612 dev_info_ratelimited(hdev->dev,
4617 hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL;
4618 hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get();
4619 dev_info_ratelimited(hdev->dev,
4624 dev_err(hdev->dev, "Received invalid clock change event %d\n",
4629 mutex_unlock(&hdev->clk_throttling.lock);
4632 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4637 struct goya_device *goya = hdev->asic_specific;
4640 dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
4671 goya_print_irq_info(hdev, event_type, false);
4672 if (hdev->hard_reset_on_fw_events)
4673 hl_device_reset(hdev, (HL_DRV_RESET_HARD |
4678 goya_print_irq_info(hdev, event_type, false);
4679 if (hdev->hard_reset_on_fw_events)
4680 hl_device_reset(hdev, HL_DRV_RESET_HARD);
4710 goya_print_irq_info(hdev, event_type, true);
4711 goya_unmask_irq(hdev, event_type);
4724 goya_print_irq_info(hdev, event_type, false);
4725 goya_unmask_irq(hdev, event_type);
4732 goya_print_clk_change_info(hdev, event_type);
4733 goya_unmask_irq(hdev, event_type);
4737 goya_print_irq_info(hdev, event_type, false);
4738 goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
4739 if (hdev->hard_reset_on_fw_events)
4740 hl_device_reset(hdev, HL_DRV_RESET_HARD);
4742 hl_fw_unmask_irq(hdev, event_type);
4746 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4752 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
4754 struct goya_device *goya = hdev->asic_specific;
4765 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
4777 cb = hl_cb_kernel_create(hdev, cb_size, false);
4807 job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
4809 dev_err(hdev->dev, "Failed to allocate a new job\n");
4822 hl_debugfs_add_job(hdev, job);
4824 rc = goya_send_job_on_qman0(hdev, job);
4826 hl_debugfs_remove_job(hdev, job);
4832 hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle);
4837 int goya_context_switch(struct hl_device *hdev, u32 asid)
4839 struct asic_fixed_properties *prop = &hdev->asic_prop;
4841 u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
4847 rc = goya_memset_device_memory(hdev, addr, size, val, false);
4849 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
4866 goya_clear_sm_regs(hdev);
4871 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
4873 struct asic_fixed_properties *prop = &hdev->asic_prop;
4874 struct goya_device *goya = hdev->asic_specific;
4882 return goya_memset_device_memory(hdev, addr, size, 0, true);
4885 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
4887 struct goya_device *goya = hdev->asic_specific;
4888 u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
4895 return goya_memset_device_memory(hdev, addr, size, val, true);
4898 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
4900 struct asic_fixed_properties *prop = &hdev->asic_prop;
4901 struct goya_device *goya = hdev->asic_specific;
4909 rc = hl_mmu_map_page(hdev->kernel_ctx,
4914 dev_err(hdev->dev, "Map failed for address 0x%llx\n",
4920 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4921 rc = hl_mmu_map_page(hdev->kernel_ctx,
4923 hdev->cpu_accessible_dma_address,
4927 dev_err(hdev->dev,
4934 rc = hl_mmu_map_page(hdev->kernel_ctx,
4936 hdev->cpu_accessible_dma_address + cpu_off,
4939 dev_err(hdev->dev,
4947 goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID);
4948 goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID);
4961 if (hl_mmu_unmap_page(hdev->kernel_ctx,
4964 dev_warn_ratelimited(hdev->dev,
4969 if (hl_mmu_unmap_page(hdev->kernel_ctx,
4972 dev_warn_ratelimited(hdev->dev,
4979 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
4981 struct asic_fixed_properties *prop = &hdev->asic_prop;
4982 struct goya_device *goya = hdev->asic_specific;
4994 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4995 if (hl_mmu_unmap_page(hdev->kernel_ctx,
4998 dev_warn(hdev->dev,
5002 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5006 dev_warn_ratelimited(hdev->dev,
5012 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5015 dev_warn_ratelimited(hdev->dev,
5022 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
5024 struct goya_device *goya = hdev->asic_specific;
5031 dev_crit(hdev->dev, "asid %u is too big\n", asid);
5037 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
5040 static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
5043 struct goya_device *goya = hdev->asic_specific;
5048 hdev->reset_info.hard_reset_pending)
5055 if (hdev->pldm)
5064 hdev,
5074 static int goya_mmu_invalidate_cache_range(struct hl_device *hdev,
5081 return hl_mmu_invalidate_cache(hdev, is_hard, flags);
5084 int goya_send_heartbeat(struct hl_device *hdev)
5086 struct goya_device *goya = hdev->asic_specific;
5091 return hl_fw_send_heartbeat(hdev);
5094 int goya_cpucp_info_get(struct hl_device *hdev)
5096 struct goya_device *goya = hdev->asic_specific;
5097 struct asic_fixed_properties *prop = &hdev->asic_prop;
5104 rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
5114 dev_err(hdev->dev,
5131 static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
5210 static void goya_hw_queues_lock(struct hl_device *hdev)
5213 struct goya_device *goya = hdev->asic_specific;
5218 static void goya_hw_queues_unlock(struct hl_device *hdev)
5221 struct goya_device *goya = hdev->asic_specific;
5226 static u32 goya_get_pci_id(struct hl_device *hdev)
5228 return hdev->pdev->device;
5231 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5234 struct goya_device *goya = hdev->asic_specific;
5239 return hl_fw_get_eeprom_data(hdev, data, max_size);
5242 static void goya_cpu_init_scrambler_dram(struct hl_device *hdev)
5250 goya_mmu_prepare(ctx->hdev, ctx->asid);
5260 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
5265 static u32 goya_get_signal_cb_size(struct hl_device *hdev)
5270 static u32 goya_get_wait_cb_size(struct hl_device *hdev)
5275 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
5281 static u32 goya_gen_wait_cb(struct hl_device *hdev,
5287 static void goya_reset_sob(struct hl_device *hdev, void *data)
5292 static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group)
5297 u64 goya_get_device_time(struct hl_device *hdev)
5309 static int goya_collective_wait_create_jobs(struct hl_device *hdev,
5321 static int goya_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
5327 static int goya_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
5333 static void goya_enable_events_from_fw(struct hl_device *hdev)
5339 static int goya_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask)
5358 static int goya_gen_sync_to_engine_map(struct hl_device *hdev,
5372 struct hl_device *hdev,
5381 struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
5397 static void goya_state_dump_init(struct hl_device *hdev)
5400 hdev->state_dump_specs.props = goya_state_dump_specs_props;
5401 hdev->state_dump_specs.funcs = goya_state_dump_funcs;
5404 static u32 goya_get_sob_addr(struct hl_device *hdev, u32 sob_id)
5414 static int goya_get_monitor_dump(struct hl_device *hdev, void *data)
5419 static void goya_check_if_razwi_happened(struct hl_device *hdev)
5423 static int goya_scrub_device_dram(struct hl_device *hdev, u64 val)
5428 static int goya_set_dram_properties(struct hl_device *hdev)
5433 static int goya_set_binning_masks(struct hl_device *hdev)
5438 static int goya_send_device_activity(struct hl_device *hdev, bool open)
5543 * @*hdev: pointer to hl_device structure
5546 void goya_set_asic_funcs(struct hl_device *hdev)
5548 hdev->asic_funcs = &goya_funcs;