Lines Matching refs:base
2774 static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)
2818 * Both RR types start blocking from base address 0x1000007FF8000000
2822 WREG32(base + reg_min_offset, write_min);
2823 WREG32(base + reg_max_offset, write_max);
2857 block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE;
2865 block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE;
2878 block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2882 block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2886 block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2987 static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)
3048 WREG32(base + min_lo_reg_offset, lower_32_bits(val_min));
3049 WREG32(base + min_hi_reg_offset, upper_32_bits(val_min));
3050 WREG32(base + max_lo_reg_offset, lower_32_bits(val_max));
3051 WREG32(base + max_hi_reg_offset, upper_32_bits(val_max));
3085 block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE;
3093 block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE;
3101 block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE;
3131 static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,
3162 WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min));
3163 WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min));
3164 WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max));
3165 WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max));