Lines Matching defs:hdev
2602 static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,
2607 hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec,
2611 static int gaudi2_init_pb_tpc(struct hl_device *hdev)
2629 hl_secure_block(hdev, glbl_sec, block_array_size);
2630 hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs,
2637 hl_unsecure_registers(hdev,
2645 hl_unsecure_registers(hdev,
2654 hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0,
2661 hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0,
2670 gaudi2_iterate_tpcs(hdev, &tpc_iter);
2682 static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,
2687 ctx->rc = hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1,
2694 static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev)
2705 gaudi2_iterate_tpcs(hdev, &tpc_iter);
2710 static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)
2774 static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)
2801 dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type);
2826 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
2835 dev_err(hdev->dev, "invalid short LBW %s range register index: %u",
2843 dev_err(hdev->dev, "invalid long LBW %s range register index: %u",
2862 gaudi2_init_blocks(hdev, &block_ctx);
2870 gaudi2_init_blocks(hdev, &block_ctx);
2879 gaudi2_init_blocks(hdev, &block_ctx);
2883 gaudi2_init_blocks(hdev, &block_ctx);
2887 gaudi2_init_blocks(hdev, &block_ctx);
2890 static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)
2968 hdev->asic_prop.fw_security_enabled)
2971 gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i,
2977 gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i,
2982 static void gaudi2_init_lbw_range_registers(struct hl_device *hdev)
2984 gaudi2_init_lbw_range_registers_secure(hdev);
2987 static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)
3023 dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type);
3054 static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index,
3063 dev_err(hdev->dev, "invalid short HBW %s range register index: %u",
3071 dev_err(hdev->dev, "invalid long HBW %s range register index: %u",
3090 gaudi2_init_blocks(hdev, &block_ctx);
3098 gaudi2_init_blocks(hdev, &block_ctx);
3106 gaudi2_init_blocks(hdev, &block_ctx);
3109 static void gaudi2_init_hbw_range_registers(struct hl_device *hdev)
3126 gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i],
3131 static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,
3152 dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type);
3168 static void gaudi2_init_mmu_range_registers(struct hl_device *hdev)
3179 rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);
3180 rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address);
3186 if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
3192 gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg);
3201 * @hdev: pointer to hl_device structure
3203 static void gaudi2_init_range_registers(struct hl_device *hdev)
3205 gaudi2_init_lbw_range_registers(hdev);
3206 gaudi2_init_hbw_range_registers(hdev);
3207 gaudi2_init_mmu_range_registers(hdev);
3214 * @hdev: pointer to hl_device structure
3220 static int gaudi2_init_protection_bits(struct hl_device *hdev)
3222 struct asic_fixed_properties *prop = &hdev->asic_prop;
3229 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3235 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3242 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3247 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3256 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3261 if (!hdev->asic_prop.fw_security_enabled)
3262 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3268 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3275 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3281 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2,
3289 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3297 rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3309 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3315 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3329 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3337 rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),
3346 rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3355 rc |= gaudi2_init_pb_tpc(hdev);
3356 rc |= gaudi2_init_pb_tpc_arc(hdev);
3360 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3365 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3374 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3382 rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,
3393 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3398 if (!hdev->asic_prop.fw_security_enabled)
3399 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3405 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3414 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3418 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3423 if (!hdev->asic_prop.fw_security_enabled) {
3424 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3428 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3435 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3444 if (!hdev->asic_prop.fw_security_enabled) {
3446 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3453 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3462 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3470 rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3478 rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3481 NULL, HL_PB_NA, hdev->nic_ports_mask);
3484 rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3489 hdev->nic_ports_mask);
3492 rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3498 hdev->nic_ports_mask);
3501 rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3507 hdev->nic_ports_mask);
3511 rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT,
3519 rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED,
3526 rc |= gaudi2_init_pb_sm_objs(hdev);
3534 * @hdev: pointer to hl_device structure
3539 int gaudi2_init_security(struct hl_device *hdev)
3543 rc = gaudi2_init_protection_bits(hdev);
3547 gaudi2_init_range_registers(hdev);
3557 static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,
3562 hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3565 hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3569 static void gaudi2_ack_pb_tpc(struct hl_device *hdev)
3580 gaudi2_iterate_tpcs(hdev, &tpc_iter);
3588 * @hdev: pointer to hl_device structure
3594 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)
3596 struct asic_fixed_properties *prop = &hdev->asic_prop;
3602 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3607 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3614 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3618 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3627 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3629 if (!hdev->asic_prop.fw_security_enabled)
3630 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3634 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3639 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3643 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3648 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3654 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3664 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3669 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3681 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3687 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3694 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3701 gaudi2_ack_pb_tpc(hdev);
3705 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3709 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3713 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3716 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3723 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3725 if (!hdev->asic_prop.fw_security_enabled)
3726 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3730 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3737 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3739 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3741 if (!hdev->asic_prop.fw_security_enabled) {
3742 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3744 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3749 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3755 if (!hdev->asic_prop.fw_security_enabled) {
3757 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3763 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,
3769 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC,
3775 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3781 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3786 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3787 gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);
3790 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3792 hdev->nic_ports_mask);
3795 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3797 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);
3800 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3802 hdev->nic_ports_mask);
3806 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3810 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3818 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
3854 dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr,