Lines Matching refs:hmmu_id
5554 bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id)
5559 hw_cap = HW_CAP_DCORE0_DMMU0 << (NUM_OF_HMMU_PER_DCORE * dcore_id + hmmu_id);
5568 static inline u32 get_hmmu_stlb_base(int dcore_id, int hmmu_id)
5572 offset = (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);
5612 int dcore_id, int hmmu_id,
5615 u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id);
5621 int dcore_id, int hmmu_id,
5624 u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id);
5632 int dcore_id, hmmu_id;
5636 for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE ; hmmu_id++) {
5637 if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
5640 gaudi2_hmmu_invalidate_cache_trigger(hdev, dcore_id, hmmu_id, inv_params);
5646 for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE ; hmmu_id++) {
5649 if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
5652 rc = gaudi2_hmmu_invalidate_cache_status_poll(hdev, dcore_id, hmmu_id,
5858 int hmmu_id)
5866 dmmu_seq = NUM_OF_HMMU_PER_DCORE * dcore_id + hmmu_id;
5876 offset = (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);
5911 int rc, dcore_id, hmmu_id;
5914 for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) {
5915 rc = gaudi2_dcore_hmmu_init(hdev, dcore_id, hmmu_id);