Lines Matching refs:asic_prop
2138 struct asic_fixed_properties *prop = &hdev->asic_prop;
2183 struct asic_fixed_properties *prop = &hdev->asic_prop;
2216 struct asic_fixed_properties *prop = &hdev->asic_prop;
2271 struct asic_fixed_properties *prop = &hdev->asic_prop;
2493 if (hdev->asic_prop.iatu_done_by_fw)
2519 if (hdev->asic_prop.iatu_done_by_fw)
2583 struct asic_fixed_properties *prop = &hdev->asic_prop;
2604 struct asic_fixed_properties *prop = &hdev->asic_prop;
2662 struct asic_fixed_properties *prop = &hdev->asic_prop;
2689 struct asic_fixed_properties *prop = &hdev->asic_prop;
2706 struct asic_fixed_properties *prop = &hdev->asic_prop;
2748 struct asic_fixed_properties *prop = &hdev->asic_prop;
2791 hdev->asic_prop.faulty_dram_cluster_map = 0;
2805 hdev->asic_prop.hmmu_hif_enabled_mask = GAUDI2_HIF_HMMU_FULL_MASK;
2812 struct asic_fixed_properties *prop = &hdev->asic_prop;
2851 struct asic_fixed_properties *prop = &hdev->asic_prop;
2933 hdev->asic_prop.psoc_timestamp_frequency = pll_freq_arr[3];
2940 struct asic_fixed_properties *prop = &hdev->asic_prop;
2974 hdev->asic_prop.iatu_done_by_fw = false;
2976 hdev->asic_prop.iatu_done_by_fw = true;
3007 kfree(hdev->asic_prop.hw_queues_props);
3013 kfree(hdev->asic_prop.hw_queues_props);
3073 hdev->asic_prop.engine_core_interrupt_reg_addr =
3148 hdev->asic_prop.supports_advanced_cpucp_rc = true;
3318 struct asic_fixed_properties *prop = &hdev->asic_prop;
3342 region->region_size = hdev->asic_prop.dram_size;
3351 struct asic_fixed_properties *prop = &hdev->asic_prop;
3396 struct asic_fixed_properties *prop = &hdev->asic_prop;
3419 struct asic_fixed_properties *prop = &hdev->asic_prop;
3531 struct asic_fixed_properties *prop = &hdev->asic_prop;
3661 struct asic_fixed_properties *prop = &hdev->asic_prop;
4151 struct asic_fixed_properties *prop = &hdev->asic_prop;
4274 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = 0 ; j < hdev->asic_prop.user_interrupt_count;
4285 struct asic_fixed_properties *prop = &hdev->asic_prop;
4307 k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) {
4336 if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit)))
4376 if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit)))
4773 struct asic_fixed_properties *prop = &hdev->asic_prop;
5094 struct asic_fixed_properties *prop = &hdev->asic_prop;
5199 struct asic_fixed_properties *prop = &hdev->asic_prop;
5372 if (!hdev->asic_prop.tpc_enabled_mask)
5425 if (!hdev->asic_prop.decoder_enabled_mask)
5435 if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit)))
5450 if (!(hdev->asic_prop.decoder_enabled_mask & BIT(dec_bit)))
5741 struct asic_fixed_properties *prop = &hdev->asic_prop;
5860 struct asic_fixed_properties *prop = &hdev->asic_prop;
5957 if (hdev->asic_prop.iatu_done_by_fw)
6096 if (hdev->asic_prop.hard_reset_done_by_fw)
6112 if (hdev->asic_prop.hard_reset_done_by_fw) {
6239 driver_performs_reset = !hdev->asic_prop.hard_reset_done_by_fw;
6249 !hdev->asic_prop.fw_security_enabled);
6646 struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
6658 asic_prop->sram_user_base_address,
6659 asic_prop->sram_end_address))
6664 asic_prop->dram_user_base_address,
6665 asic_prop->dram_end_address))
6671 asic_prop->dmmu.start_addr,
6672 asic_prop->dmmu.end_addr))
6678 asic_prop->pmmu.start_addr,
6679 asic_prop->pmmu.end_addr) ||
6683 asic_prop->pmmu_huge.start_addr,
6684 asic_prop->pmmu_huge.end_addr))
6868 return hdev->asic_prop.first_available_user_sob[0] +
7017 struct asic_fixed_properties *prop = &hdev->asic_prop;
7228 struct asic_fixed_properties *prop = &hdev->asic_prop;
7256 struct asic_fixed_properties *prop = &hdev->asic_prop;
7451 struct asic_fixed_properties *prop = &hdev->asic_prop;
7612 struct asic_fixed_properties *prop = &hdev->asic_prop;
7962 !hdev->asic_prop.fw_security_enabled &&
8097 struct asic_fixed_properties *prop = &hdev->asic_prop;
9903 (hdev->asic_prop.fw_security_enabled && is_critical))
9917 if (hdev->asic_prop.fw_security_enabled && is_critical) {
9967 struct asic_fixed_properties *prop = &hdev->asic_prop;
9977 sob_offset = hdev->asic_prop.first_available_user_sob[0] * 4;
10082 struct asic_fixed_properties *prop = &hdev->asic_prop;
10096 struct asic_fixed_properties *prop = &hdev->asic_prop;
10130 offset = hdev->asic_prop.first_available_cq[0] * 4;
10172 offset = hdev->asic_prop.first_available_user_mon[0] * 4;
10194 offset = hdev->asic_prop.first_available_user_sob[0] * 4;
10496 struct asic_fixed_properties *prop = &hdev->asic_prop;
10512 struct asic_fixed_properties *prop = &hdev->asic_prop;
10562 int index = cs->sequence & (hdev->asic_prop.max_pending_cs - 1);
10790 struct asic_fixed_properties *prop = &hdev->asic_prop;
10810 struct asic_fixed_properties *prop = &hdev->asic_prop;
11101 struct asic_fixed_properties *prop = &hdev->asic_prop;