Lines Matching defs:stlb_base
5463 u32 stlb_base, u32 asid, u64 phys_addr)
5473 WREG32(stlb_base + STLB_ASID_OFFSET, asid);
5474 WREG32(stlb_base + STLB_HOP0_PA43_12_OFFSET, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
5475 WREG32(stlb_base + STLB_HOP0_PA63_44_OFFSET, phys_addr >> MMU_HOP0_PA63_44_SHIFT);
5476 WREG32(stlb_base + STLB_BUSY_OFFSET, 0x80000000);
5480 stlb_base + STLB_BUSY_OFFSET,
5494 static void gaudi2_mmu_send_invalidate_cache_cmd(struct hl_device *hdev, u32 stlb_base,
5505 WREG32(stlb_base + start_offset, inv_start_val);
5508 static int gaudi2_mmu_invalidate_cache_status_poll(struct hl_device *hdev, u32 stlb_base,
5545 stlb_base + start_offset,
5576 static void gaudi2_mmu_invalidate_cache_trigger(struct hl_device *hdev, u32 stlb_base,
5592 WREG32(stlb_base + STLB_RANGE_INV_START_LSB_OFFSET,
5595 WREG32(stlb_base + STLB_RANGE_INV_START_MSB_OFFSET,
5598 WREG32(stlb_base + STLB_RANGE_INV_END_LSB_OFFSET,
5601 WREG32(stlb_base + STLB_RANGE_INV_END_MSB_OFFSET,
5607 gaudi2_mmu_send_invalidate_cache_cmd(hdev, stlb_base, start_offset,
5615 u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id);
5617 gaudi2_mmu_invalidate_cache_trigger(hdev, stlb_base, inv_params);
5624 u32 stlb_base = get_hmmu_stlb_base(dcore_id, hmmu_id);
5626 return gaudi2_mmu_invalidate_cache_status_poll(hdev, stlb_base, inv_params);
5739 static int gaudi2_mmu_update_hop0_addr(struct hl_device *hdev, u32 stlb_base)
5752 rc = gaudi2_mmu_update_asid_hop0_addr(hdev, stlb_base, asid, hop0_addr);
5762 static int gaudi2_mmu_init_common(struct hl_device *hdev, u32 mmu_base, u32 stlb_base)
5772 WREG32(stlb_base + STLB_INV_ALL_START_OFFSET, 1);
5776 stlb_base + STLB_SRAM_INIT_OFFSET,
5785 rc = gaudi2_mmu_update_hop0_addr(hdev, stlb_base);
5793 stlb_base + STLB_INV_ALL_START_OFFSET,
5810 u32 mmu_base, stlb_base;
5817 stlb_base = mmPMMU_HBW_STLB_BASE;
5819 RMWREG32_SHIFTED(stlb_base + STLB_HOP_CONFIGURATION_OFFSET,
5831 WREG32(stlb_base + STLB_LL_LOOKUP_MASK_63_32_OFFSET, 0);
5848 rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base);
5862 u32 offset, mmu_base, stlb_base, hw_cap;
5878 stlb_base = mmDCORE0_HMMU0_STLB_BASE + offset;
5883 RMWREG32_SHIFTED(stlb_base + STLB_HOP_CONFIGURATION_OFFSET,
5895 RMWREG32(stlb_base + STLB_HOP_CONFIGURATION_OFFSET, 1,
5900 rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base);