Lines Matching defs:reg_val
3079 u32 reg_base, reg_val;
3103 reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 1);
3104 WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val);
3113 reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 0);
3114 WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val);
3852 u32 reg_val;
3854 reg_val = FIELD_PREP(PDMA0_CORE_CFG_1_HALT_MASK, 0x1);
3855 WREG32(reg_base + DMA_CORE_CFG_1_OFFSET, reg_val);
3923 u32 reg_val;
3929 reg_val = FIELD_PREP(ROT_MSS_HALT_WBC_MASK, 0x1) |
3937 WREG32(mmROT0_MSS_HALT + i * ROT_OFFSET, reg_val);
4324 u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1);
4343 WREG32(mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL + offset, reg_val);
4364 u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1);
4383 WREG32(mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL + offset, reg_val);
4418 u32 reg_base, reg_val;
4422 reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK, 1);
4424 reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK, 1);
4426 WREG32(reg_base + ARC_HALT_REQ_OFFSET, reg_val);
4527 u32 reg_base, reg_addr, reg_val, tpc_id;
4538 reg_val = FIELD_PREP(DCORE0_TPC0_CFG_TPC_STALL_V_MASK,
4540 WREG32(reg_addr, reg_val);
4554 u32 reg_base, reg_addr, reg_val, mme_id;
4562 reg_val = FIELD_PREP(DCORE0_MME_CTRL_LO_QM_STALL_V_MASK,
4564 WREG32(reg_addr, reg_val);
4572 u32 reg_base, reg_addr, reg_val, edma_id;
4583 reg_val = FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_HALT_MASK,
4585 WREG32(reg_addr, reg_val);
4588 reg_val = FIELD_PREP(DCORE0_EDMA0_CORE_CFG_1_HALT_MASK, 0x1) |
4590 WREG32(reg_addr, reg_val);
5222 u32 reg_val;
5226 reg_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK, 1);
5227 reg_val |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_LBW_EN_MASK, 1);
5230 WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + (4 * i), reg_val);
5233 reg_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_CQ_EN_MASK, 1);
5234 WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + (4 * i), reg_val);
5264 u32 reg_val;
5267 reg_val = FIELD_PREP(MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK, 0);
5268 reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_POS_INF_MASK, 1);
5269 reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_NEG_INF_MASK, 1);
5270 reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_SRC_NAN_MASK, 1);
5271 reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_RESULT_POS_INF_MASK, 1);
5272 reg_val |= FIELD_PREP(MME_ACC_INTR_MASK_AP_RESULT_NEG_INF_MASK, 1);
5274 WREG32(reg_base + MME_ACC_INTR_MASK_OFFSET, reg_val);
6131 u32 reg_val;
6137 reg_val,
6138 reg_val == CPU_RST_STATUS_SOFT_RST_DONE,
6144 reg_val);
6199 u32 reg_val;
6208 reg_val,
6209 reg_val == 0,
6214 dev_err(hdev->dev, "Timeout while waiting for device to reset 0x%x\n", reg_val);
7453 u32 vdec_id, i, ports_offset, reg_val;
7479 reg_val = (asid << DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_SHIFT) |
7481 WREG32(mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID + dcore_offset, reg_val);
7548 u32 reg_base, reg_offset, reg_val = 0;
7553 reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_ARC_REGION_CFG_MMU_BP_MASK, 0);
7554 reg_val |= FIELD_PREP(ARC_FARM_ARC0_AUX_ARC_REGION_CFG_0_ASID_MASK, asid);
7557 WREG32(reg_base + reg_offset, reg_val);
7560 WREG32(reg_base + reg_offset, reg_val);
7563 WREG32(reg_base + reg_offset, reg_val);
7566 WREG32(reg_base + reg_offset, reg_val);
7569 WREG32(reg_base + reg_offset, reg_val);
7572 WREG32(reg_base + reg_offset, reg_val);
7575 WREG32(reg_base + reg_offset, reg_val);
7578 WREG32(reg_base + reg_offset, reg_val);
7581 WREG32(reg_base + reg_offset, reg_val);
7584 WREG32(reg_base + reg_offset, reg_val);
7587 WREG32(reg_base + reg_offset, reg_val);