Lines Matching defs:mmu_base
5762 static int gaudi2_mmu_init_common(struct hl_device *hdev, u32 mmu_base, u32 stlb_base)
5789 WREG32(mmu_base + MMU_BYPASS_OFFSET, 0);
5802 WREG32(mmu_base + MMU_ENABLE_OFFSET, 1);
5810 u32 mmu_base, stlb_base;
5816 mmu_base = mmPMMU_HBW_MMU_BASE;
5835 RMWREG32_SHIFTED(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET,
5846 WREG32(mmu_base + MMU_SPI_SEI_MASK_OFFSET, GAUDI2_PMMU_SPI_SEI_ENABLE_MASK);
5848 rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base);
5862 u32 offset, mmu_base, stlb_base, hw_cap;
5877 mmu_base = mmDCORE0_HMMU0_MMU_BASE + offset;
5880 RMWREG32(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET, 5 /* 64MB */,
5898 WREG32(mmu_base + MMU_SPI_SEI_MASK_OFFSET, GAUDI2_HMMU_SPI_SEI_ENABLE_MASK);
5900 rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base);
8835 static void gaudi2_handle_page_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu,
8841 valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));
8846 val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE));
8849 addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA));
8863 WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);
8866 static void gaudi2_handle_access_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu)
8871 valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));
8876 val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE));
8879 addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA));
8886 WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);
8890 u64 mmu_base, bool is_pmmu, u64 *event_mask)
8895 spi_sei_cause = RREG32(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET);
8903 gaudi2_handle_page_error(hdev, mmu_base, is_pmmu, event_mask);
8905 gaudi2_handle_access_error(hdev, mmu_base, is_pmmu);
8915 WREG32_AND(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET, ~spi_sei_cause);
8918 WREG32(mmu_base + MMU_INTERRUPT_CLR_OFFSET, interrupt_clr);
9074 u64 mmu_base;
9079 mmu_base = get_hmmu_base(event_type);
9085 mmu_base = mmPMMU_HBW_MMU_BASE;
9091 if (mmu_base == ULONG_MAX)
9094 error_count = gaudi2_handle_mmu_spi_sei_generic(hdev, event_type, mmu_base,
10918 static int gaudi2_get_mmu_base(struct hl_device *hdev, u64 mmu_id, u32 *mmu_base)
10922 *mmu_base = mmDCORE0_HMMU0_MMU_BASE;
10925 *mmu_base = mmDCORE0_HMMU1_MMU_BASE;
10928 *mmu_base = mmDCORE0_HMMU2_MMU_BASE;
10931 *mmu_base = mmDCORE0_HMMU3_MMU_BASE;
10934 *mmu_base = mmDCORE1_HMMU0_MMU_BASE;
10937 *mmu_base = mmDCORE1_HMMU1_MMU_BASE;
10940 *mmu_base = mmDCORE1_HMMU2_MMU_BASE;
10943 *mmu_base = mmDCORE1_HMMU3_MMU_BASE;
10946 *mmu_base = mmDCORE2_HMMU0_MMU_BASE;
10949 *mmu_base = mmDCORE2_HMMU1_MMU_BASE;
10952 *mmu_base = mmDCORE2_HMMU2_MMU_BASE;
10955 *mmu_base = mmDCORE2_HMMU3_MMU_BASE;
10958 *mmu_base = mmDCORE3_HMMU0_MMU_BASE;
10961 *mmu_base = mmDCORE3_HMMU1_MMU_BASE;
10964 *mmu_base = mmDCORE3_HMMU2_MMU_BASE;
10967 *mmu_base = mmDCORE3_HMMU3_MMU_BASE;
10970 *mmu_base = mmPMMU_HBW_MMU_BASE;
10983 u32 mmu_base;
10988 if (gaudi2_get_mmu_base(hdev, mmu_id, &mmu_base))
10991 gaudi2_handle_page_error(hdev, mmu_base, is_pmmu, NULL);
10992 gaudi2_handle_access_error(hdev, mmu_base, is_pmmu);